[S] Change in coreboot[master]: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68866 )

Change subject: soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE
......................................................................

soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE

Currently the GPP clk req configuration code assumes that the size of
the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that
code to use the `ARRAY_SIZE` macro instead.

BRANCH=guybrush
BUG=b:250009974
TEST=Ran on nipperkin device, verified that clk req settings are
correct.

Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7
Signed-off-by: Robert Zieba 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Felix Held 
---
M src/soc/amd/cezanne/fch.c
1 file changed, 25 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 7227d20..1ceb8bc 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -153,7 +153,8 @@

uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);

-	pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT);
+	pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
+					    ARRAY_SIZE(cfg->gpp_clk_config));
    for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
    	gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);