Attention is currently required from: Alexander Couzens, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email )
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ......................................................................
Patch Set 7:
(3 comments)
File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80343/comment/037c66ce_4eb7cfa3 : PS5, Line 14: register "PcieRpClkSrcNumber[0]" = "0"
Since I don't have a x16 device, I tested it with a x1 device and it worked. […]
Sounds fine. But please leave a comment in the dt that we use the PcieRp* settings because there is no equivalent for the PEG.
https://review.coreboot.org/c/coreboot/+/80343/comment/c780ebfd_581e6d58 : PS5, Line 51: register "PcieRpClkReqSupport[4]" = "false"
If I remember correctly you suggested to disable it on the IRC when I was having issues with PCI err […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/80343/comment/948b79cb_01649bef : PS5, Line 112: # Vendor values dumped using util/superiotool.
I was able to get better results figuring out which LDN was which if I looked at 7h of each LDN inst […]
Actually, I don't get it. 7h is where pnp_set_logical_device() stores the number... Something probably went off in the dumping code. If this code works it works :)