Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent

[Subrata Banik (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Andrey Petrov, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60441 )

Change subject: soc/intel/alderlake: Add option to make MRC log silent
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Patch Set 2:

(1 comment)

Patchset:

PS2:
> Why not map the console loglevel to this UPD? That would avoid adding more Kconfigs.

This is what my understanding is:

1. coreboot and FSP MRC log level are different for example: typical log level for coreboot is 8 where else for MRC the most verbose level is 5.

Hence, the UPD assignment like below will set the wrong value to UPD. Isn't it?
m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;

2. Most of the time, we want to see FSP debug logs but not that verbose MRC debug log which takes several minutes to boot the platform hence, we might still prefer to have different log levels between coreboot and FSP. And for that matter inside FSP even there are 2 different log level (there is one more UPD PcdSerialDebugLevel which controls overall FSP entire debug log level). But the intention is to just make FSP-M silent without additional MRC training prints.

May be we can drop `SOC_INTEL_ALDERLAKE_MRC_DEBUG_CONSENT` config and assign the UPD like this ?

if (CONFIG(SILENT_FSP_M_DEBUG_MESSAGE))
     m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0;
else
     m_cfg->SerialDebugMrcLevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3;

in that way, we can reduce to only 1 new Kconfig rather SoC wise Kconfig. WDYT?