[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

[David Wu (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik.

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email )

Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
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mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

Set PCIe root port 4 speed to Gen2 for WIFI 7

BUG=b:374205496
TEST=Boot to OS and then check link speed.
     Use command: lspci -vv | grep 'LnkSta'

Before
     LnkSta: Speed 8GT/s (downgraded), Width x1
     After
     LnkSta: Speed 5GT/s (downgraded), Width x1

Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu 
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85520/1

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 9f62d27..a191052 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -487,6 +487,7 @@
    			.clk_src = 2,
    			.clk_req = 2,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_pcie_speed = 2,
    		}"
    		chip drivers/wifi/generic
    			register "wake" = "GPE0_DW1_03"