Change in coreboot[master]: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQ...

[Saurabh Mishra (Code Review)]

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60176 )

Change subject: src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls. src/soc/intel/alderlake/fsp_params.c : Commented out the call. Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers.
......................................................................

src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS &
UPD calls.
src/soc/intel/alderlake/fsp_params.c : Commented out the call.
Meminit function call in coreboot has been updated as per new FSP UPD and DQS in
headers.

change-Id: I0c6ae72610da39fc18ff252c440d006e83c573b1
Signed-off-by: Saurabh Mishra 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/meminit.c
2 files changed, 17 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/60176/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 251b252..5d8559b 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -642,7 +642,7 @@
    for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
    	fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);

-	s_cfg->LpmStateEnableMask = get_supported_lpm_mask();
+	//s_cfg->LpmStateEnableMask = get_supported_lpm_mask();

/* Apply minimum assertion width settings */
    if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index d81e856..026bdcc 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -123,14 +123,14 @@
 static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
    uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
-		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
-		[1] = { &mem_cfg->MemorySpdPtr002, &mem_cfg->MemorySpdPtr003, },
-		[2] = { &mem_cfg->MemorySpdPtr004, &mem_cfg->MemorySpdPtr005, },
-		[3] = { &mem_cfg->MemorySpdPtr006, &mem_cfg->MemorySpdPtr007, },
-		[4] = { &mem_cfg->MemorySpdPtr008, &mem_cfg->MemorySpdPtr009, },
-		[5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
-		[6] = { &mem_cfg->MemorySpdPtr012, &mem_cfg->MemorySpdPtr013, },
-		[7] = { &mem_cfg->MemorySpdPtr014, &mem_cfg->MemorySpdPtr015, },
+		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, },
+		[1] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, },
+		[2] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, },
+		[3] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, },
+		[4] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr000, },
+		[5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, },
+		[6] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, },
+		[7] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr010, },
    };
    uint8_t *disable_channel_upds[MRC_CHANNELS] = {
    	&mem_cfg->DisableMc0Ch0,
@@ -183,10 +183,10 @@
    	&mem_cfg->DqMapCpu2DramMc0Ch1,
    	&mem_cfg->DqMapCpu2DramMc0Ch2,
    	&mem_cfg->DqMapCpu2DramMc0Ch3,
-		&mem_cfg->DqMapCpu2DramMc0Ch4,
-		&mem_cfg->DqMapCpu2DramMc0Ch5,
-		&mem_cfg->DqMapCpu2DramMc0Ch6,
-		&mem_cfg->DqMapCpu2DramMc0Ch7,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
    };

const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
@@ -204,10 +204,10 @@
    	&mem_cfg->DqsMapCpu2DramMc0Ch1,
    	&mem_cfg->DqsMapCpu2DramMc0Ch2,
    	&mem_cfg->DqsMapCpu2DramMc0Ch3,
-		&mem_cfg->DqsMapCpu2DramMc0Ch4,
-		&mem_cfg->DqsMapCpu2DramMc0Ch5,
-		&mem_cfg->DqsMapCpu2Drammc0Ch6,
-		&mem_cfg->DqsMapCpu2DramMc0Ch7,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
    };

const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);