Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68898 )
Change subject: mb/google/brask/variants/moli: keep SAGV disable ......................................................................
mb/google/brask/variants/moli: keep SAGV disable
Since there is not too many low power requirement for moli and it is doing FSI firmware qual, so it is not critical to enable the SAGV and keep SAGV disable.
BUG=b:254600066 TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi raihow_shi@wistron.corp-partner.google.com Change-Id: I4115b35fed35b74a307b08f7a10ebced2309297f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68898 Reviewed-by: Zhuohao Lee zhuohao@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Derek Huang derekhuang@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 20 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Zhuohao Lee: Looks good to me, approved Raihow Shi: Looks good to me, but someone else must approve Derek Huang: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 5612b6e..2d35e14 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -14,7 +14,6 @@ end end chip soc/intel/alderlake - register "sagv" = "SaGv_Enabled" # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2 register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,