Change in coreboot[master]: vendorcode/google/chromeos: Introduce helper for CSE board reset
Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Build and boot the drawcia to OS.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/1
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index f48069f..4dc6000 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -92,5 +92,14 @@ to ACPI DSD table in device driver. These parameters will be applied by kernel driver through device property at boot.
+config CHROMEOS_CSE_BOARD_RESET_OVERRIDE + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + On some boards that run old firmware version in cr50, Embedded Controller (EC) needs + to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW. + Enabling this config will help to override the default global reset. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index a25700f..fd9398e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -10,6 +10,7 @@ ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c +ramstage-$(CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
bootblock-y += watchdog.c verstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c new file mode 100644 index 0000000..0768e6d --- /dev/null +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <cf9_reset.h> +#include <ec/google/chromeec/ec.h> +#include <halt.h> +#include <intelblocks/cse.h> + +void cse_board_reset(void) +{ + /* TODO: Check tpm firmware version before initiating AP reset. */ + dcache_clean_all(); + outb(FULL_RST | SYS_RST, RST_CNT); + if (!google_chromeec_ap_reset()) + halt(); +} +
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#2).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Build and boot the drawcia to OS.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/2/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44646/2/src/vendorcode/google/chrom... PS2, Line 13: ramstage-$(CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c Add CONFIG_
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#3).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Build and boot the drawcia to OS.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/2/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44646/2/src/vendorcode/google/chrom... PS2, Line 13: ramstage-$(CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
Add CONFIG_
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 14: FULL_RST | SYS_RST It might be helpful to have a comment indicating that this is to ensure that AP makes a trip to S5 (i.e. full power reset) when SYSRST# is asserted by the EC.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 14: FULL_RST | SYS_RST
It might be helpful to have a comment indicating that this is to ensure that AP makes a trip to S5 ( […]
Also, usually port 0xcf9 needs time to settle between the request and the command to perform the reset type so should we add the usual 50uS delay after this to quiesce?
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3: Code-Review+2
I would be comfortable with merging this immediately as-is as this blocks us and any minor comments be fixed up as a follow up.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 15: if (!google_chromeec_ap_reset()) Sorry, I forgot to add in the last review that we should perhaps do a version check here now that is possible since Jes's work made it in https://review.coreboot.org/c/coreboot/+/43741
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 14: FULL_RST | SYS_RST
Also, usually port 0xcf9 needs time to settle between the request and the command to perform the res […]
Just setting the 4th bit is sufficient in the coreboot. This will just configure system to cold reset type which is sufficient. ``` outb(FULL_RST, RST_CNT). ```
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#4).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/4
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 4: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 14: FULL_RST | SYS_RST
Just setting the 4th bit is sufficient in the coreboot. […]
@Sridhar, I will check with that and upload a follow-up patch.
@Edward, EC commands have a longer latency than 50 us and we are using that for the command to 0xcf9 to settle down.
@Furquan, Added the comment as required.
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 15: if (!google_chromeec_ap_reset())
Sorry, I forgot to add in the last review that we should perhaps do a version check here now that is […]
Done
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 4: Code-Review+2
Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#5).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/5
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom... PS3, Line 14: FULL_RST | SYS_RST
@Sridhar, I will check with that and upload a follow-up patch. […]
Done
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5: Code-Review+2
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5: Code-Review+2
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5: Code-Review+1
Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... PS5, Line 101: . so that cr50 resets the TPM state. This is required on boards where the cr50 firmware does not understand the new strap used (currently applicable only to boards using strap 0xe).
Hello Sam McNally, build bot (Jenkins), Daniel Kurtz, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#6).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/6
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 6: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... PS5, Line 101: .
so that cr50 resets the TPM state. […]
I think it would be good to add the above to help text as well just to make it clear why this Kconfig is used.
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 25: if (version.epoch != 0 || version.major != 0 || version.minor > 22) : return; : We should get a confirmation about this from Mary/Namyoon.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 7: Code-Review+2
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 25: if (version.epoch != 0 || version.major != 0 || version.minor > 22) : return; :
We should get a confirmation about this from Mary/Namyoon.
From the release notes, it's 0.{3,4}.25 or later.
Mary Ruthven has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 25: if (version.epoch != 0 || version.major != 0 || version.minor > 22) : return; :
From the release notes, it's 0.{3,4}.25 or later.
We modified the defaults in 0.{3,4}.20, so straps with a PU on DIOA1 would default to PLT_RST even if they aren't in the cr50 strap table. so 3/4.20 are the first images the strap support.
Hello Sam McNally, build bot (Jenkins), Daniel Kurtz, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#8).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/8
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 8: Code-Review+2
Hello Sam McNally, build bot (Jenkins), Daniel Kurtz, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#9).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/9
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/44646/5/src/vendorcode/google/chrom... PS5, Line 101: .
I think it would be good to add the above to help text as well just to make it clear why this Kconfi […]
Done
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 25: if (version.epoch != 0 || version.major != 0 || version.minor > 22) : return; :
We modified the defaults in 0.{3,4}. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 9: Code-Review+2
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 9: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 21: verions nit: versions
Hello Sam McNally, build bot (Jenkins), Daniel Kurtz, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44646
to look at the new patch set (#10).
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44646/10
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/6/src/vendorcode/google/chrom... PS6, Line 21: verions
nit: versions
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 10: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 10: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 10: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 10: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset.
BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/cse_board_reset.c 3 files changed, 50 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index f48069f..0528d00 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -92,5 +92,16 @@ to ACPI DSD table in device driver. These parameters will be applied by kernel driver through device property at boot.
+config CHROMEOS_CSE_BOARD_RESET_OVERRIDE + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + On some boards that run old firmware version in cr50, Embedded Controller (EC) needs + to trigger the cold reset of Application Processor (AP) when CSE jumps from RO to RW + so that cr50 resets the TPM state. This is required on boards where the cr50 firmware + does not understand the new cr50 strap config (applicable only to boards using strap + config 0xe). Enabling this config will help to override the default global reset. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index a25700f..b429d6b 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -10,6 +10,7 @@ ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c +ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
bootblock-y += watchdog.c verstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c new file mode 100644 index 0000000..6034f0d --- /dev/null +++ b/src/vendorcode/google/chromeos/cse_board_reset.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <drivers/spi/tpm/tpm.h> +#include <ec/google/chromeec/ec.h> +#include <halt.h> +#include <intelblocks/cse.h> +#include <security/tpm/tss.h> + +void cse_board_reset(void) +{ + struct cr50_firmware_version version; + + /* Initialize TPM and get the cr50 firmware version. */ + tlcl_lib_init(); + cr50_get_firmware_version(&version); + /* + * Cr50 firmware versions 0.[3|4].20 or newer support strap config 0xe where PLTRST from + * AP is connected to cr50's PLTRST# signal. So return immediately and trigger a + * global reset. + */ + if (version.epoch != 0 || version.major > 4 || + (version.major >= 3 && version.minor >= 20)) + return; + + printk(BIOS_INFO, "Initiating request to EC to trigger cold reset\n"); + /* + * Clean the data cache and set the full reset bit, so that when EC toggles + * SYS_RESET# pin, AP makes a trip to S5 and then to S0. + */ + dcache_clean_all(); + outb(FULL_RST, RST_CNT); + if (!google_chromeec_ap_reset()) + halt(); +}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset ......................................................................
Patch Set 11:
Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16146 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16145 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/16144 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16143 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/16142 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/16148 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/16147
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Daniel Kurtz (Code Review)
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Edward O'Callaghan (Code Review)
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Furquan Shaikh (Code Review)
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Karthik Ramasubramanian (Code Review)
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Mary Ruthven (Code Review)
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Nick Vaccaro (Code Review)
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Sam McNally (Code Review)
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Sridhar Siricilla (Code Review)
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Tim Wawrzynczak (Code Review)