Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57019 )
Change subject: WIP: Herobrine: Fix i2c TPM communication errors ......................................................................
WIP: Herobrine: Fix i2c TPM communication errors
Signed-off-by: Shelley Chen shchen@google.com Change-Id: Ia0d4236b01a604a100a40e5b4ea94ec2ab06372e --- M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/herobrine/chromeos.c 4 files changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/57019/1
diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 6afcc4d..f3f391a 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -52,6 +52,9 @@ hex default 0xC
+config DRIVER_TPM_I2C_ADDR + default 0x50 + config DRIVER_TPM_SPI_BUS depends on MAINBOARD_HAS_SPI_TPM_CR50 hex diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h index 33c8c7d..77a7d0f 100644 --- a/src/mainboard/google/herobrine/board.h +++ b/src/mainboard/google/herobrine/board.h @@ -7,6 +7,7 @@ #include <gpio.h>
#define GPIO_SD_CD_L GPIO(91) +#define GPIO_H1_AP_INT GPIO(54)
#define QCOM_SC7280_SKU1 0x0 #define QCOM_SC7280_SKU2 0x1 diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c index 69a46da..6dc76d2 100644 --- a/src/mainboard/google/herobrine/bootblock.c +++ b/src/mainboard/google/herobrine/bootblock.c @@ -2,12 +2,13 @@
#include <bootblock_common.h> #include "board.h" +#include <soc/qupv3_i2c_common.h> #include <soc/qcom_qup_se.h> #include <soc/qupv3_spi_common.h>
void bootblock_mainboard_init(void) { setup_chromeos_gpios(); - qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); /* H1/TPM SPI */ + i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ } diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index 643dcc2..1f482dc 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -3,10 +3,12 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> #include "board.h" +#include <security/tpm/tis.h>
void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); }
void fill_lb_gpios(struct lb_gpios *gpios) @@ -14,7 +16,14 @@ struct lb_gpio chromeos_gpios[] = { {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), "SD card detect"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, };
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_H1_AP_INT); +}