Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42156 )
Change subject: nb/intel/x4x: Drop unused `pci_ops.h` include ......................................................................
nb/intel/x4x: Drop unused `pci_ops.h` include
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: I58162865d596574b8a52447624f0102b8dceefa4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/x4x/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42156/1
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 5f47359..5a30a80 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h>
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42156 )
Change subject: nb/intel/x4x: Drop unused `pci_ops.h` include ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42156 )
Change subject: nb/intel/x4x: Drop unused `pci_ops.h` include ......................................................................
nb/intel/x4x: Drop unused `pci_ops.h` include
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: I58162865d596574b8a52447624f0102b8dceefa4 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42156 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/x4x/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved
diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index 5f47359..5a30a80 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h>
-
Angel Pons (Code Review) -
Felix Held (Code Review)
-
HAOUAS Elyes (Code Review)