[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz

[Paul Menzel (Code Review)]

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yidi Lin, Yu-Ping Wu.

Paul Menzel has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )

Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
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Patch Set 12:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84298/comment/65e5547f_bb36e3e3?usp... :
PS9, Line 13: measure eMMC clock ok
            :
> https://partnerissuetracker.corp.google.com/issues/356578805#comment26 […]

I am denied access to that URL. Commit messages need to be self-contained. It’d be great if you added it.

Commit Message:

https://review.coreboot.org/c/coreboot/+/84298/comment/d37e3ed7_41344af7?usp... :
PS12, Line 11: When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and the frequency division value to 125. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set the source clock frequency correctly, we can get the correct frequency division value, and then get the correct clock output.
Please add a blank line between paragraphs, and re-flow it for 72 characters per line.

File src/soc/mediatek/common/msdc.c:

https://review.coreboot.org/c/coreboot/+/84298/comment/2a133c7c_222bd9f8?usp... :
PS9, Line 432: 	host->src_hz = 400 * 1000 * 1000;
Mengqi, thank you for the explanation. Please also update the summary then. Maybe:
> Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz