Change in coreboot[master]: mb/google/brya/variants/brask: disabled autonomous GPIO power management

[Zhuohao Lee (Code Review)]

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60100 )

Change subject: mb/google/brya/variants/brask: disabled autonomous GPIO power management
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mb/google/brya/variants/brask: disabled autonomous GPIO power management

We found that the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the cr50
firmware to the 0.6.70. Besides, we also need to avoid the factory
power on issue when using the 0.3.22 cr50 firmware. So, we submitted
this patch to disable the gpio power management.

BUG=b:210540890
TEST=reboot 100 cycles without the error message.

Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee 
---
M src/mainboard/google/brya/variants/brask/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60100/1

diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 63a683d..3d9e7b1 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -1,4 +1,14 @@
 chip soc/intel/alderlake
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
    device domain 0 on
    	device ref dtt on
    		chip drivers/intel/dptf