[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver

[Jarried Lin (Code Review)]

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email )

Change subject: soc/mediatek/mt8196: Add pwrsel driver
......................................................................

soc/mediatek/mt8196: Add pwrsel driver

The MediaTek pwrsel (Power Select) mainly used to reduce power
consumption, controlled by mcupm.

BUG=b:317009620
TEST=build pass, reg set ok, log show:
PWR_SEL = 0x0

Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18
Signed-off-by: Jarried Lin 
---
M src/mainboard/google/rauru/romstage.c
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h
A src/soc/mediatek/mt8196/mtk_pwrsel.c
5 files changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85613/1

diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c
index ebeedb8..b6f0d4e 100644
--- a/src/mainboard/google/rauru/romstage.c
+++ b/src/mainboard/google/rauru/romstage.c
@@ -3,11 +3,13 @@
 #include <arch/stages.h>
 #include <soc/emi.h>
 #include <soc/irq2axi.h>
+#include <soc/mtk_pwrsel.h>
 #include <soc/pcie.h>

void platform_romstage_main(void)
 {
    irq2axi_disable();
+	pwrsel_init();
    mtk_dram_init();

if (CONFIG(PCI))
diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 9652a1e..728b180 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -30,6 +30,7 @@
 romstage-y += ../common/memory.c memory.c
 romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
+romstage-y += mtk_pwrsel.c
 romstage-y += ../common/mt6363.c mt6363.c
 romstage-y += ../common/mt6373.c mt6373.c
 romstage-y += ../common/pmif_clk.c pmif_clk.c
diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h
index cc57292..c9fb302 100644
--- a/src/soc/mediatek/mt8196/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h
@@ -8,6 +8,7 @@
    MCUPM_CFG_BASE		= 0x0C240000,
    BUS_TRACE_MONITOR_BASE	= 0x0D040000,
    IO_PHYS			= 0x10000000,
+	MFGSYS_BASE		= 0x40000000,
 };

enum {
diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h
new file mode 100644
index 0000000..7e5ac1a
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__
+#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__
+
+#include <soc/addressmap.h>
+
+#define VAL_PWRSEL		0x0
+#define VAL_PWRSEL_AUTO_MODE	0x1FF0000
+#define OFFSET_PWRSEL		0x04A0
+#define OFFSET_PWRSEL_AUTO_MODE_CFG	0x04A4
+
+#define MFG_VCORE_AO_CFG_BASE		(MFGSYS_BASE + 0x0B860000)		/* 0x4B860000 */
+#define MFG_VCORE_AO_RPC_PWRSEL_CONFIG	(MFG_VCORE_AO_CFG_BASE + 0x00B4)	/* 0x4B8600B4 */
+
+void pwrsel_init(void);
+
+#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */
diff --git a/src/soc/mediatek/mt8196/mtk_pwrsel.c b/src/soc/mediatek/mt8196/mtk_pwrsel.c
new file mode 100644
index 0000000..91a7496
--- /dev/null
+++ b/src/soc/mediatek/mt8196/mtk_pwrsel.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/mtk_pwrsel.h>
+
+static void cpu_pwrsel_init(void)
+{
+	write32p(MCUSYS_BASE + OFFSET_PWRSEL, VAL_PWRSEL);
+	write32p(MCUSYS_BASE + OFFSET_PWRSEL_AUTO_MODE_CFG, VAL_PWRSEL_AUTO_MODE);
+}
+
+static void gpu_pwrsel_init(void)
+{
+	write32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG, (GENMASK(14, 0)));
+}
+
+void pwrsel_init(void)
+{
+	cpu_pwrsel_init();
+	gpu_pwrsel_init();
+	printk(BIOS_INFO, "PWR_SEL = %#x\n",
+	       read32p(MCUSYS_BASE + OFFSET_PWRSEL));
+	printk(BIOS_INFO, "PWRSEL_CONFIG = %#x\n",
+	       read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG));
+}