Change in ...coreboot[master]: mb/google/hatch/variants: Add DPTF based Fan control

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31980

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

mb/google/hatch/variants: Add DPTF based Fan control

This adds DPTF based Fan speed control for CML based Hatch system.

BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures

Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
1 file changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31980/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
index 6e818f6..f1b14ff 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -15,18 +15,34 @@

#define DPTF_CPU_PASSIVE	95
 #define DPTF_CPU_CRITICAL	105
+#define DPTF_CPU_ACTIVE_AC0	87
+#define DPTF_CPU_ACTIVE_AC1	85
+#define DPTF_CPU_ACTIVE_AC2	83
+#define DPTF_CPU_ACTIVE_AC3	80
+#define DPTF_CPU_ACTIVE_AC4	75

#define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
 #define DPTF_TSR0_PASSIVE	65
 #define DPTF_TSR0_CRITICAL	75
+#define DPTF_TSR0_ACTIVE_AC0	50
+#define DPTF_TSR0_ACTIVE_AC1	47
+#define DPTF_TSR0_ACTIVE_AC2	45
+#define DPTF_TSR0_ACTIVE_AC3	42
+#define DPTF_TSR0_ACTIVE_AC4	39

#define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor 2"
 #define DPTF_TSR1_PASSIVE	65
 #define DPTF_TSR1_CRITICAL	75
+#define DPTF_TSR1_ACTIVE_AC0    50
+#define DPTF_TSR1_ACTIVE_AC1    47
+#define DPTF_TSR1_ACTIVE_AC2    45
+#define DPTF_TSR1_ACTIVE_AC3    42
+#define DPTF_TSR1_ACTIVE_AC4    39

#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL

/* Charger performance states, board-specific values from charger and EC */
 Name (CHPS, Package () {
@@ -36,6 +52,49 @@
    Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
 })

+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	}
+})
+#endif
+
 Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
    Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31980 )

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
PS1, Line 55: #ifdef DPTF_ENABLE_FAN_CONTROL
Let's not add this since it is defined just a few lines up.

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
PS1, Line 84: B0D4
TCPU?

[Sumeet R Pawnikar (Code Review)]

Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31980

to look at the new patch set (#2).

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

mb/google/hatch/variants: Add DPTF based Fan control

This adds DPTF based Fan speed control for CML based Hatch system.

BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures

Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
1 file changed, 58 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31980/2

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31980 )

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
PS1, Line 55: #ifdef DPTF_ENABLE_FAN_CONTROL
> Let's not add this since it is defined just a few lines up.

Done

https://review.coreboot.org/#/c/31980/1/src/mainboard/google/hatch/variants/... 
PS1, Line 84: B0D4
> TCPU?

Thanks. I have corrected this.

[Sumeet R Pawnikar (Code Review)]

Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31980

to look at the new patch set (#3).

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

mb/google/hatch/variants: Add DPTF based Fan control

This adds DPTF based Fan speed control for CML based Hatch system.

BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures

Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
1 file changed, 57 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31980/3

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31980 )

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/#/c/31980/3/src/mainboard/google/hatch/variants/... 
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:

https://review.coreboot.org/#/c/31980/3/src/mainboard/google/hatch/variants/... 
PS3, Line 59: TODO
Do you want to raise a bug for that?

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31980 )

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/31980/3/src/mainboard/google/hatch/variants/... 
File src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl:

https://review.coreboot.org/#/c/31980/3/src/mainboard/google/hatch/variants/... 
PS3, Line 59: TODO
> Do you want to raise a bug for that?

Once we will have closed chassis system, we will work on tuning these values.

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31980 )

Change subject: mb/google/hatch/variants: Add DPTF based Fan control
......................................................................

mb/google/hatch/variants: Add DPTF based Fan control

This adds DPTF based Fan speed control for CML based Hatch system.

BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures

Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
1 file changed, 57 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
index 6e818f6..1384ccf 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -15,18 +15,34 @@

#define DPTF_CPU_PASSIVE	95
 #define DPTF_CPU_CRITICAL	105
+#define DPTF_CPU_ACTIVE_AC0	87
+#define DPTF_CPU_ACTIVE_AC1	85
+#define DPTF_CPU_ACTIVE_AC2	83
+#define DPTF_CPU_ACTIVE_AC3	80
+#define DPTF_CPU_ACTIVE_AC4	75

#define DPTF_TSR0_SENSOR_ID	1
 #define DPTF_TSR0_SENSOR_NAME	"Thermal Sensor 1"
 #define DPTF_TSR0_PASSIVE	65
 #define DPTF_TSR0_CRITICAL	75
+#define DPTF_TSR0_ACTIVE_AC0	50
+#define DPTF_TSR0_ACTIVE_AC1	47
+#define DPTF_TSR0_ACTIVE_AC2	45
+#define DPTF_TSR0_ACTIVE_AC3	42
+#define DPTF_TSR0_ACTIVE_AC4	39

#define DPTF_TSR1_SENSOR_ID	2
 #define DPTF_TSR1_SENSOR_NAME	"Thermal Sensor 2"
 #define DPTF_TSR1_PASSIVE	65
 #define DPTF_TSR1_CRITICAL	75
+#define DPTF_TSR1_ACTIVE_AC0    50
+#define DPTF_TSR1_ACTIVE_AC1    47
+#define DPTF_TSR1_ACTIVE_AC2    45
+#define DPTF_TSR1_ACTIVE_AC3    42
+#define DPTF_TSR1_ACTIVE_AC4    39

#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL

/* Charger performance states, board-specific values from charger and EC */
 Name (CHPS, Package () {
@@ -36,6 +52,47 @@
    Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
 })

+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+	0,	// Revision
+	/*
+	 * TODO : Need to update this Table after characterization.
+	 *	  These are initial reference values.
+	 */
+	/* Control, Trip Point, Speed, NoiseLevel, Power */
+	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
+	Package () {80,		0xFFFFFFFF,	5800,	180,	1800},
+	Package () {70,		0xFFFFFFFF,	5000,	145,	1450},
+	Package () {60,		0xFFFFFFFF,	4900,	115,	1150},
+	Package () {50,		0xFFFFFFFF,	3838,	90,	900},
+	Package () {40,		0xFFFFFFFF,	2904,	55,	550},
+	Package () {30,		0xFFFFFFFF,	2337,	30,	300},
+	Package () {20,		0xFFFFFFFF,	1608,	15,	150},
+	Package () {10,		0xFFFFFFFF,	800,	10,	100},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
+})
+
+Name (DART, Package () {
+	/* Fan effect on CPU */
+	0,	// Revision
+	Package () {
+		/*
+		 * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+		 *	AC7, AC8, AC9
+		 */
+		_SB.DPTF.TFN1, _SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
+	}
+})
+
 Name (DTRT, Package () {
    /* CPU Throttle Effect on CPU */
    Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },