Change in coreboot[master]: nb/intel/ironlake: Do not call `collect_system_info` twice

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49581 )

Change subject: nb/intel/ironlake: Do not call `collect_system_info` twice
......................................................................

nb/intel/ironlake: Do not call `collect_system_info` twice

Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.

Tested on out-of-tree HP 630, still boots.

Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/raminit.c
1 file changed, 7 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49581/1

diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index d64adef..ca40443 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1480,16 +1480,6 @@
    int i;
    unsigned int channel;

-	/* Wait for some bit, maybe TXT clear. */
-	while (!(read8((u8 *)0xfed40000) & (1 << 7)))
-		;
-
-	if (!info->memory_reserved_for_heci_mb) {
-		/* Wait for ME to be ready */
-		intel_early_me_init();
-		info->memory_reserved_for_heci_mb = intel_early_me_uma_size();
-	}
-
    for (i = 0; i < 3; i++) {
    	capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2));
    	printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]);
@@ -3733,16 +3723,18 @@
    info.training.reg_178 = 0;
    info.training.reg_10b = 0;

-	info.memory_reserved_for_heci_mb = 0;
+	/* Wait for some bit, maybe TXT clear. */
+	while (!(read8((u8 *)0xfed40000) & (1 << 7)))
+		;
+
+	/* Wait for ME to be ready */
+	intel_early_me_init();
+	info.memory_reserved_for_heci_mb = intel_early_me_uma_size();

/* before SPD */
    timestamp_add_now(101);

if (!s3resume || 1) {	// possible error
-		pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2);	// = 0x80
-
-		collect_system_info(&info);
-
    	memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));

info.use_ecc = 1;