Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55294 )
Change subject: soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Are we sure this wasn't a documentation error? Seems strange they would change the hardware like tha […]
i also find this change to be rather unexpected, but i was told that the cezanne ppr matches the hardware design and those definitions are also consistent with the ppr of some other newer socs; the change seems to be between picasso and renoir. i have verified that the cezanne ppr matches the hardware register definitions and that the reference code for picasso and cezanne ends up writing the same bit pattern into the register. no idea what the reason for this definition change was. the register and bit definitions part of the ppr is generated from the register and bit definitions, so it's very unlikely that the register and bit documentation won't be consistent with the hardware design. also haven't found any bug in those parts of the pprs yet, so i'll just treat that as the main reference