Patch set updated for coreboot: 1f4dcf3 armv7: Allow accessing ACTLR (Auxiliary Control Register)

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4447

-gerrit

commit 1f4dcf39e1310e79475a4c55392f1f4d37d5ade5
Author: Hung-Te Lin 
Date:   Thu Aug 8 11:07:40 2013 +0800

armv7: Allow accessing ACTLR (Auxiliary Control Register)

The ACTLR provides implementation defined configuration and control options for
    the processor.

Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311
    Signed-off-by: Hung-Te Lin 
    Reviewed-on: https://gerrit.chromium.org/gerrit/65107
    Commit-Queue: Gabe Black 
---
 src/arch/armv7/include/arch/cpu.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h
index efd2dc9..2613025 100644
--- a/src/arch/armv7/include/arch/cpu.h
+++ b/src/arch/armv7/include/arch/cpu.h
@@ -66,6 +66,20 @@ inline static uint32_t read_mpidr(void)
    return value;
 }

+/* read Auxiliary Control Register (ACTLR) */
+inline static uint32_t read_actlr(void)
+{
+	uint32_t val = 0;
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
+	return val;
+}
+
+/* write Auxiliary Control Register (ACTLR) */
+inline static void write_actlr(uint32_t val)
+{
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
+}
+
 /* wait for interrupt. */
 inline static void wfi(void)
 {