Change in coreboot[master]: amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21493

Change subject: amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup
......................................................................

amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup

Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits.  The code has no effect on modern
Family 15h APUs.  The bits being modified come up set out of reset.

Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/model_15_init.c
1 file changed, 0 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/21493/1

diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index 631e89c..7dfcdb8 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -37,9 +37,6 @@
    u8 i;
    msr_t msr;
    int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	u32 siblings;
-#endif

disable_cache();
    /* Enable access to AMD RdDram and WrDram extension bits */
@@ -71,30 +68,13 @@
    for (i = 0 ; i < 6 ; i++)
    	wrmsr(MCI_STATUS + (i * 4), msr);

-
    /* Enable the local CPU APICs */
    setup_lapic();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif

/* DisableCf8ExtCfg */
    msr = rdmsr(NB_CFG_MSR);
    msr.hi &= ~(1 << (46 - 32));
    wrmsr(NB_CFG_MSR, msr);
-

/* Write protect SMM space with SMMLOCK. */
    msr = rdmsr(HWCR_MSR);