Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ......................................................................
Patch Set 10:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/d3a215e1_3dc83cd8 PS10, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/04767d70_642fc733 PS10, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/3fe98d0e_d2908f5c PS10, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/b5d4a1bb_e13206bc PS10, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/f1531f06_bb90cbf9 PS10, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10); line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/caa37326_f042d72d PS10, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/d667b70a_1614e9c7 PS10, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/c78c95aa_23dc2c4f PS10, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/965d6e98_3ce94650 PS10, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/85578ce3_d22ab0d0 PS10, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/c130b01c_cc5369d5 PS10, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/c7074cd1_50ba87cf PS10, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/78aa79f2_a619993f PS10, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/c47ca34f_e3fa44c7 PS10, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130137): https://review.coreboot.org/c/coreboot/+/57886/comment/8a23a179_51f6d0dc PS10, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); line over 96 characters