Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74593 )
Change subject: mb/google/myst: Add named GPIO's ......................................................................
mb/google/myst: Add named GPIO's
Add named GPIO's to help prevent confusion in GPIO management
BUG=b:278969100 TEST=builds
Signed-off-by: Jon Murphy jpmurphy@google.com Change-Id: I6832316d704959f61fe05b9bb23f449e562af7ed --- M src/mainboard/google/myst/chromeos.c M src/mainboard/google/myst/ec.c M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/myst/variants/myst/include/variant/gpio.h 7 files changed, 180 insertions(+), 158 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74593/1
diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c index e488e81..5c10f65 100644 --- a/src/mainboard/google/myst/chromeos.c +++ b/src/mainboard/google/myst/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h>
void fill_lb_gpios(struct lb_gpios *gpios) {}
diff --git a/src/mainboard/google/myst/ec.c b/src/mainboard/google/myst/ec.c index 060119d..d8c1ae3 100644 --- a/src/mainboard/google/myst/ec.c +++ b/src/mainboard/google/myst/ec.c @@ -3,9 +3,9 @@ #include <acpi/acpi.h> #include <amdblocks/smi.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/smi.h> #include <variant/ec.h> +#include <variant/gpio.h>
static const struct sci_source espi_sci_sources[] = { { diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 0add7a0..4cdb4bc 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -1,171 +1,108 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <gpio.h> +#include <variant/gpio.h>
/* GPIO configuration in ramstage*/ static const struct soc_amd_gpio base_gpio_table[] = { - /* PWR_BTN_L */ - PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), - /* SYS_RESET_L */ - PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* WAKE_L */ - PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* Unused */ + PAD_NF(EC_SOC_PWR_BTN_ODL, PWR_BTN_L, PULL_NONE), + PAD_NF(SYS_RST_ODL, SYS_RESET_L, PULL_NONE), + PAD_NF_SCI(SOC_PCIE_WAKE_ODL, WAKE_L, PULL_NONE, EDGE_LOW), + /* GPIO_3 Unused */ PAD_NC(GPIO_3), - /* EN_PWR_FP */ - PAD_GPO(GPIO_4, LOW), - /* EN_PP3300_TCHPAD */ - PAD_GPO(GPIO_5, HIGH), - /* EN_PP3300_WWAN_X */ - PAD_GPO(GPIO_6, LOW), - /* SOC_PEN_DETECT_ODL */ - PAD_WAKE(GPIO_7, PULL_NONE, EDGE_LOW, S0i3), - /* SOC_TCHPAD_INT_ODL */ - PAD_SCI(GPIO_8, PULL_NONE, LEVEL_LOW), - /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_9, HIGH), - /* WWAN_RST */ - PAD_GPO(GPIO_11, LOW), - /* Unused */ + PAD_GPO(EN_PWR_FP, LOW), + PAD_GPO(EN_PP3300_TCHPAD_X, HIGH), + PAD_GPO(EN_PP3300_WWAN_X, LOW), + PAD_WAKE(SOC_PEN_DETECT_ODL, PULL_NONE, EDGE_LOW, S0i3), + PAD_SCI(SOC_TCHPAD_INT_ODL, PULL_NONE, LEVEL_LOW), + PAD_GPO(EN_PP3300_WLAN_X, HIGH), + PAD_GPO(WWAN_RST, LOW), + /* GPIO_12 Unused */ PAD_NC(GPIO_12), - /* GPIO_13 - GPIO_15: Not available */ - /* USB_OC0_L */ - PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), - /* EC_SOC_WAKE_R_ODL */ - PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), - /* FP_SOC_INT_L */ - PAD_SCI(GPIO_18, PULL_NONE, LEVEL_LOW), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* Unused */ + PAD_NF(USB_FAULT_ODL, USB_OC0_L, PULL_NONE), + PAD_SCI(EC_SOC_WAKE_R_ODL, PULL_UP, EDGE_LOW), + PAD_SCI(FP_SOC_INT_L, PULL_NONE, LEVEL_LOW), + PAD_NF(I2C_SOC_AUDIO_HDMI_SCL_U, I2C3_SCL, PULL_NONE), + PAD_NF(I2C_SOC_AUDIO_HDMI_SDA_U, I2C3_SDA, PULL_NONE), + /* GPIO_21 Unused */ PAD_NC(GPIO_21), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), - /* AC_PRES */ - PAD_NF(GPIO_23, AC_PRES, PULL_NONE), - /* Unused */ + PAD_NF(ESPI_EC_ALERT_SOC_ODL, ESPI_ALERT_D1, PULL_NONE), + PAD_NF(SOC_AC_PRES_OD, AC_PRES, PULL_NONE), + /* GPIO_24 Unused */ PAD_NC(GPIO_24), - /* GPIO_25-26: Not available */ - /* SOC_PCIE_RST1_R_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), - /* GPIO_28: Not available */ - /* SD_AUX_RST */ - PAD_GPO(GPIO_29, LOW), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* SSD_AUX_RST */ - PAD_GPO(GPIO_31, LOW), - /* LPC_RST_L */ - PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), - /* GPIO_33 - GPIO_37: Not available */ - /* WLAN_AUX_RST_L */ - PAD_GPO(GPIO_38, HIGH), - /* WWAN_AUX_RST_L */ - PAD_GPO(GPIO_39, HIGH), - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_40, HIGH), - /* GPIO_41 - GPIO_66: Not available */ - /* GPIO_67 (Unused) */ + PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH), + PAD_NFO(SOC_PCIE_RST1_R_L, PCIE_RST1_L, HIGH), + PAD_GPO(SD_AUX_RST, LOW), + PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE), + PAD_GPO(SSD_AUX_RST, LOW), + PAD_NF(LPC_RST_L_MB, LPC_RST_L, PULL_NONE), + PAD_GPO(WLAN_AUX_RST_L, HIGH), + PAD_GPO(WWAN_AUX_RST_L, HIGH), + PAD_GPO(SOC_FP_RST_L, HIGH), + PAD_GPI(SOC_MEM_VID_C1, PULL_NONE), + /* GPIO_67 Unused */ PAD_NC(GPIO_67), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), - /* SOC_CLK_FPMCU_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), - /* EN_TCHSCR_REPORT */ - PAD_GPO(GPIO_74, LOW), - /* SOC_CLK_FPMCU_R_L TODO(276939271): Selectively init */ - PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), - /* Unused */ + PAD_NF(ESPI_SOC_D2_EC_R, SPI1_DAT2, PULL_NONE), + PAD_NF(ESPI_SOC_D3_EC_R, SPI1_DAT3, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_CLK_FPMCU_R, SPI2_CLK, PULL_NONE), + PAD_GPO(EN_TCHSCR_REPORT, LOW), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_CS_FPMCU_R_L, SPI2_CS1_L, PULL_NONE), + /* GPIO_76 Unused */ PAD_NC(GPIO_76), - /* ESPI_SOC_CLK_EC_R */ - PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), - /* RAM_ID_0 */ - PAD_GPI(GPIO_78, PULL_NONE), - /* RAM_ID_1 */ - PAD_GPI(GPIO_79, PULL_NONE), - /* ESPI_SOC_D1_EC_R */ - PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), - /* ESPI_SOC_D0_EC_R */ - PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ + PAD_NF(ESPI_SOC_CLK_EC_R, SPI1_CLK, PULL_NONE), + PAD_GPI(RAM_ID_0, PULL_NONE), + PAD_GPI(RAM_ID_1, PULL_NONE), + PAD_NF(ESPI_SOC_D1_EC_R, SPI1_DAT1, PULL_NONE), + PAD_NF(ESPI_SOC_D0_EC_R, SPI1_DAT0, PULL_NONE), + PAD_INT(GSC_SOC_INT_ODL, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* GPIO_85 Unused */ PAD_NC(GPIO_85), - /* HP_INT_ODL */ - PAD_GPI(GPIO_89, PULL_NONE), - /* EC_SOC_INT_ODL */ - PAD_GPI(GPIO_90, PULL_NONE), - /* TCHSCR_INT_ODL */ - PAD_GPI(GPIO_91, PULL_NONE), - /* CLK_REQ0_L / WLAN */ - PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), - /* SPI_SOC_DO_FPMCU_DI_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), - /* SPI_SOC_DI_FPMCU_DO_R TODO(276939271): Selectively init */ - PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), - /* RAM_ID_2 */ - PAD_GPI(GPIO_106, PULL_NONE), - /* RAM_ID_3 */ - PAD_GPI(GPIO_107, PULL_NONE), - /* I2C2_SCL */ - PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), - /* I2C2_SDA */ - PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), - /* CLK_REQ1_L / SD */ - PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), - /* CLK_REQ2_L / WWAN */ - PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), - /* Unused */ + PAD_GPI(HP_INT_ODL, PULL_NONE), + PAD_GPI(EC_SOC_INT_ODL, PULL_NONE), + PAD_GPI(TCHSCR_INT_ODL, PULL_NONE), + PAD_NF(PCIE_0_WLAN_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_DO_FPMCU_DI_R, SPI2_DAT0, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(SPI_SOC_DI_FPMCU_DO_R, SPI2_DAT1, PULL_NONE), + PAD_GPI(RAM_ID_2, PULL_NONE), + PAD_GPI(RAM_ID_3, PULL_NONE), + PAD_NF(I2C_SOC_GSC_SCL_U, I2C2_SCL, PULL_NONE), + PAD_NF(I2C_SOC_GSC_SDA_U, I2C2_SDA, PULL_NONE), + PAD_NF(PCIE_1_SD_CLKREQ_ODL, CLK_REQ1_L, PULL_NONE), + PAD_NF(PCIE_2_WWAN_CLKREQ_ODL, CLK_REQ2_L, PULL_NONE), + /* GPIO_130 Unused */ PAD_NC(GPIO_130), - /* CLK_REQ3_L / SSD */ - PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), - /* SOC_FP_BOOT0 */ - PAD_GPO(GPIO_132, LOW), - /* EN_PP3300_CAM */ - PAD_GPO(GPIO_135, HIGH), - /* Unused */ + PAD_NF(PCIE_3_SSD_CLKREQ_ODL, CLK_REQ3_L, PULL_NONE), + PAD_GPO(SOC_FP_BOOT0, LOW), + PAD_GPO(EN_PP3300_CAM_X, HIGH), + /* GPIO_136 Unused */ PAD_NC(GPIO_136), - /* Unused */ + /* GPIO_137 Unused */ PAD_NC(GPIO_137), - /* Unused */ + /* GPIO_138 Unused */ PAD_NC(GPIO_138), - /* SOC_BIOS_WP_OD */ - PAD_GPI(GPIO_139, PULL_NONE), - /* UART1_TXD / FPMCU TODO(276939271): Selectively init */ - PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), - /* UART0_RXD / DBG */ - PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), - /* UART1_RXD / FPMCU TODO(276939271): Selectively init */ - PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), - /* UART0_TXD / DBG */ - PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_144, HIGH), - /* I2C0_SCL */ - PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), - /* I2C0_SDA */ - PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), - /* I2C1_SCL */ - PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), - /* I2C1_SDA */ - PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_153, LOW), - /* BT_DISABLE */ - PAD_GPO(GPIO_154, LOW), - /* HDMI_RST */ + PAD_GPI(SOC_BIOS_WP_OD, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(UART_SOC_TX_FPMCU_RX, UART1_TXD, PULL_NONE), + PAD_NF(UART_SOC_RX_DBG_TX, UART0_RXD, PULL_NONE), + /* TODO(276939271): Selectively init */ + PAD_NF(UART_SOC_RX_FPMCU_TX, UART1_RXD, PULL_NONE), + PAD_NF(UART_SOC_TX_DBG_RX, UART0_TXD, PULL_NONE), + PAD_GPO(EN_PP3300_TCHSCR_X, HIGH), + PAD_NF(I2C_SOC_TCHPAD_SCL, I2C0_SCL, PULL_NONE), + PAD_NF(I2C_SOC_TCHPAD_SDA, I2C0_SDA, PULL_NONE), + PAD_NF(I2C_SOC_TCHSCR_SCL, I2C1_SCL, PULL_NONE), + PAD_NF(I2C_SOC_TCHSCR_SDA, I2C1_SDA, PULL_NONE), + PAD_GPO(EN_SPKR, LOW), + PAD_GPO(BT_DISABLE, LOW), + /* GPIO_155 Unused */ PAD_GPO(GPIO_155, HIGH), - /* WLAN_DISABLE */ - PAD_GPO(GPIO_156, LOW), - /* TCHSCR_RST_L */ - PAD_GPO(GPIO_157, HIGH), + PAD_GPO(WLAN_DISABLE, LOW), + PAD_GPO(TCHSCR_RST_L, HIGH), };
/* GPIO configuration in bootblock */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h index c6ab30f..2eeb167 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h @@ -5,8 +5,7 @@
#include <ec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <baseboard/gpio.h> -#include <gpio.h> +#include <variant/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ @@ -73,9 +72,6 @@ /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO
-/* EC sync irq */ -#define EC_SYNC_IRQ GPIO_90 - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE
diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h index a6683fd..13286b1 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/gpio.h @@ -5,7 +5,78 @@
#include <gpio.h>
+#define EC_SOC_PWR_BTN_ODL GPIO_0 +#define SYS_RST_ODL GPIO_1 +#define SOC_PCIE_WAKE_ODL GPIO_2 +#define EN_PWR_FP GPIO_4 +#define EN_PP3300_TCHPAD_X GPIO_5 +#define EN_PP3300_WWAN_X GPIO_6 +#define SOC_PEN_DETECT_ODL GPIO_7 +#define SOC_TCHPAD_INT_ODL GPIO_8 +#define EN_PP3300_WLAN_X GPIO_9 +#define WWAN_RST GPIO_11 +#define USB_FAULT_ODL GPIO_16 +#define EC_SOC_WAKE_R_ODL GPIO_17 +#define FP_SOC_INT_L GPIO_18 +#define I2C_SOC_AUDIO_HDMI_SCL_U GPIO_19 +#define I2C_SOC_AUDIO_HDMI_SDA_U GPIO_20 +#define ESPI_EC_ALERT_SOC_ODL GPIO_22 +#define SOC_AC_PRES_OD GPIO_23 +#define SOC_PCIE_RST0_R_L GPIO_26 +#define SOC_PCIE_RST1_R_L GPIO_27 +#define SD_AUX_RST GPIO_29 +#define ESPI_SOC_CS_EC_R_L GPIO_30 +#define SSD_AUX_RST GPIO_31 +#define LPC_RST_L_MB GPIO_32 +#define WLAN_AUX_RST_L GPIO_38 +#define WWAN_AUX_RST_L GPIO_39 +#define SOC_FP_RST_L GPIO_40 +#define SOC_MEM_VID_C1 GPIO_42 +#define ESPI_SOC_D2_EC_R GPIO_68 +#define ESPI_SOC_D3_EC_R GPIO_69 +#define SPI_SOC_CLK_FPMCU_R GPIO_70 +#define EN_TCHSCR_REPORT GPIO_74 +#define SPI_SOC_CS_FPMCU_R_L GPIO_75 +#define ESPI_SOC_CLK_EC_R GPIO_77 +#define RAM_ID_0 GPIO_78 +#define RAM_ID_1 GPIO_79 +#define ESPI_SOC_D1_EC_R GPIO_80 +#define ESPI_SOC_D0_EC_R GPIO_81 +#define GSC_SOC_INT_ODL GPIO_84 +#define HP_INT_ODL GPIO_89 +#define EC_SOC_INT_ODL GPIO_90 +#define TCHSCR_INT_ODL GPIO_91 +#define PCIE_0_WLAN_CLKREQ_ODL GPIO_92 +#define SPI_SOC_DO_FPMCU_DI_R GPIO_104 +#define SPI_SOC_DI_FPMCU_DO_R GPIO_105 +#define RAM_ID_2 GPIO_106 +#define RAM_ID_3 GPIO_107 +#define I2C_SOC_GSC_SCL_U GPIO_113 +#define I2C_SOC_GSC_SDA_U GPIO_114 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define PCIE_2_WWAN_CLKREQ_ODL GPIO_116 +#define PCIE_3_SSD_CLKREQ_ODL GPIO_131 +#define SOC_FP_BOOT0 GPIO_132 +#define EN_PP3300_CAM_X GPIO_135 +#define SOC_BIOS_WP_OD GPIO_139 +#define UART_SOC_TX_FPMCU_RX GPIO_140 +#define UART_SOC_RX_DBG_TX GPIO_141 +#define UART_SOC_RX_FPMCU_TX GPIO_142 +#define UART_SOC_TX_DBG_RX GPIO_143 +#define EN_PP3300_TCHSCR_X GPIO_144 +#define I2C_SOC_TCHPAD_SCL GPIO_145 +#define I2C_SOC_TCHPAD_SDA GPIO_146 +#define I2C_SOC_TCHSCR_SCL GPIO_147 +#define I2C_SOC_TCHSCR_SDA GPIO_148 +#define EN_SPKR GPIO_153 +#define BT_DISABLE GPIO_154 +#define WLAN_DISABLE GPIO_156 +#define TCHSCR_RST_L GPIO_157 + +/* EC sync irq */ +#define EC_SYNC_IRQ EC_SOC_INT_ODL + /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_139 +#define CROS_WP_GPIO SOC_BIOS_WP_OD
#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 3f69548..a15a819 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__
-#include <gpio.h> +#include <variant/gpio.h>
/* This function provides base GPIO configuration table. */ diff --git a/src/mainboard/google/myst/variants/myst/include/variant/gpio.h b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/myst/variants/myst/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h>
-
Jon Murphy (Code Review)