Change in ...coreboot[master]: src/southbridge/intel/i82801gx/pcie.c: Apply clang-format cleanups

[Jacob Garber (Code Review)]

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31865

Change subject: src/southbridge/intel/i82801gx/pcie.c: Apply clang-format cleanups
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src/southbridge/intel/i82801gx/pcie.c: Apply clang-format cleanups

Apply automatic clang-format suggestions.

Signed-off-by: Jacob Garber 
Change-Id: I9c08a929e8a318ea4e90edecaa93b8794d03d735
---
M src/southbridge/intel/i82801gx/pcie.c
1 file changed, 23 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31865/1

diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 4679ee5..81679a9 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -112,11 +112,11 @@

/* Clear errors in status registers */
    reg16 = pci_read_config16(dev, 0x06);
-	//reg16 |= 0xf900;
+	// reg16 |= 0xf900;
    pci_write_config16(dev, 0x06, reg16);

reg16 = pci_read_config16(dev, 0x1e);
-	//reg16 |= 0xf900;
+	// reg16 |= 0xf900;
    pci_write_config16(dev, 0x1e, reg16);
 }

@@ -141,8 +141,7 @@

rp = root_port_number(dev);
    if (rp > rpc.num_ports) {
-		printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
-		       rp, rpc.num_ports);
+		printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports);
    	return;
    }

@@ -166,10 +165,8 @@
    new_devfn = PCI_DEVFN(ICH_PCIE_DEV_SLOT, pci_func);

if (dev->path.pci.devfn != new_devfn) {
-		printk(BIOS_DEBUG,
-		       "ICH: PCIe map %02x.%1x -> %02x.%1x\n",
-		       PCI_SLOT(dev->path.pci.devfn),
-		       PCI_FUNC(dev->path.pci.devfn),
+		printk(BIOS_DEBUG, "ICH: PCIe map %02x.%1x -> %02x.%1x\n",
+		       PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
    	       PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));

dev->path.pci.devfn = new_devfn;
@@ -182,8 +179,7 @@
    int coalesce = 0;

if (dev->chip_info != NULL) {
-		struct southbridge_intel_i82801gx_config *config
-			= dev->chip_info;
+		struct southbridge_intel_i82801gx_config *config = dev->chip_info;
    	coalesce = config->pcie_port_coalesce;
    }

@@ -196,16 +192,14 @@
    	pcie_dev = rpc.ports[i];

if (dev == NULL) {
-			printk(BIOS_ERR, "Root Port %d device is NULL?\n",
-			       i + 1);
+			printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1);
    		continue;
    	}

if (pcie_dev->enabled)
    		continue;

-		printk(BIOS_DEBUG, "%s: Disabling device\n",
-		       dev_path(pcie_dev));
+		printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev));

/* Disable this device if possible */
    	i82801gx_enable(pcie_dev);
@@ -234,8 +228,7 @@
    	}
    }

-	printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n",
-	       rpc.orig_rpfn, rpc.new_rpfn);
+	printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn);
    RCBA32(RPFN) = rpc.new_rpfn;
 }

@@ -253,16 +246,13 @@
 }

-static void pcie_set_subsystem(struct device *dev, unsigned int vendor,
-			       unsigned int device)
+static void pcie_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
 {
    /* NOTE: This is not the default position! */
    if (!vendor || !device) {
-		pci_write_config32(dev, 0x94,
-				pci_read_config32(dev, 0));
+		pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
    } else {
-		pci_write_config32(dev, 0x94,
-				((device & 0xffff) << 16) | (vendor & 0xffff));
+		pci_write_config32(dev, 0x94, ((device & 0xffff) << 16) | (vendor & 0xffff));
    }
 }

@@ -271,13 +261,13 @@
 };

static struct device_operations device_ops = {
-	.read_resources		= pci_bus_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_bus_enable_resources,
-	.init			= pci_init,
-	.enable			= ich_pcie_enable,
-	.scan_bus		= pci_scan_bridge,
-	.ops_pci		= &pci_ops,
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = pci_init,
+	.enable = ich_pcie_enable,
+	.scan_bus = pci_scan_bridge,
+	.ops_pci = &pci_ops,
 };

static const unsigned short i82801gx_pcie_ids[] = {
@@ -287,11 +277,10 @@
    0x27d6, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
    0x27e0, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
    0x27e2, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
-	0
-};
+	0};

static const struct pci_driver i82801gx_pcie __pci_driver = {
-	.ops		= &device_ops,
-	.vendor		= PCI_VENDOR_ID_INTEL,
-	.devices	= i82801gx_pcie_ids,
+	.ops = &device_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.devices = i82801gx_pcie_ids,
 };

[Jacob Garber (Code Review)]

Jacob Garber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31865 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Apply clang-format cleanups
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Abandoned