the following patch was just integrated into master: commit 76d16715ec067abcadecbbd79b51e2711b8ec57c Author: Aaron Durbin adurbin@chromium.org Date: Fri Jul 17 16:52:10 2015 -0500
skylake: add global reset cause registers to power state
Log the global reset causes in the power state structure. While working in there pack the struct and use width-specific types as this struct crosses the romstate <-> ramstage boundary. Lastly, remove hsio version as it wasn't being written or read.
After global reset induced: PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 00000000 00000000 00000000 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: d8010200 00003808 GBLRST_CAUSE: 00000000 00040004 Previous Sleep State: S0
BUG=None BRANCH=None TEST=Induced global reset on glados using ETR3 register and write to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47 Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617 Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/286640 Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: http://review.coreboot.org/11011 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net
See http://review.coreboot.org/11011 for details.
-gerrit