Change in coreboot[master]: mb/google/brya/var/taeko: Improve factory process to avoid mess up eM...

[Kevin Chang (Code Review)]

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62941 )

Change subject: mb/google/brya/var/taeko: Improve factory process to avoid mess up eMMC and SSD when first boot.
......................................................................

mb/google/brya/var/taeko: Improve factory process to avoid mess up eMMC and
SSD when first boot.

Using GPP_F19 as eMMC detect pin when first boot with default FW ID.

BUG=b:224884408
TEST=Build FW and test on rework MB also test on original MB pass.

Signed-off-by: Kevin Chang 
Change-Id: I6eb29680518ba5ba447ac16aef5eaaf0262437e0
---
M src/mainboard/google/brya/romstage.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brya/variants/taeko/Makefile.inc
M src/mainboard/google/brya/variants/taeko/gpio.c
A src/mainboard/google/brya/variants/taeko/runtimestorage.c
5 files changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/62941/1

diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c
index 4e88eca..e43e7d4 100644
--- a/src/mainboard/google/brya/romstage.c
+++ b/src/mainboard/google/brya/romstage.c
@@ -23,4 +23,9 @@

pads = variant_romstage_gpio_table(&pads_num);
    gpio_configure_pads(pads, pads_num);
+	pcieclk_override(memupd);
+}
+
+__weak void pcieclk_override(FSPM_UPD *memupd)
+{
 }
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index 9accc08..d065c96 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
@@ -17,6 +17,7 @@
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 const struct pad_config *variant_romstage_gpio_table(size_t *num);
+const struct pad_config *variant_special_gpio_table(size_t *num);

const struct mb_cfg *variant_memory_params(void);
 void variant_get_spd_info(struct mem_spd *spd_info);
@@ -24,6 +25,7 @@
 bool variant_is_half_populated(void);
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
 void variant_fill_ssdt(const struct device *dev);
+void pcieclk_override(FSPM_UPD *memupd);

enum s0ix_entry {
    S0IX_EXIT,
diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc
index 396e5be..f3b1239 100644
--- a/src/mainboard/google/brya/variants/taeko/Makefile.inc
+++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc
@@ -4,6 +4,8 @@

romstage-y += memory.c

+romstage-y += runtimestorage.c
+
 ramstage-y += gpio.c

ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c
index 2005760..69bf47a 100644
--- a/src/mainboard/google/brya/variants/taeko/gpio.c
+++ b/src/mainboard/google/brya/variants/taeko/gpio.c
@@ -206,6 +206,11 @@
    PAD_CFG_GPO(GPP_B4, 1, DEEP),
 };

+static const struct pad_config special_gpio_table[] = {
+	/* F19 : SRCCLKREQ6# ==> eMMC_detect */
+	PAD_CFG_GPI(GPP_F19, NONE, DEEP),
+};
+
 const struct pad_config *variant_gpio_override_table(size_t *num)
 {
    *num = ARRAY_SIZE(override_gpio_table);
@@ -223,3 +228,9 @@
    *num = ARRAY_SIZE(romstage_gpio_table);
    return romstage_gpio_table;
 }
+
+const struct pad_config *variant_special_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(special_gpio_table);
+	return special_gpio_table;
+}
diff --git a/src/mainboard/google/brya/variants/taeko/runtimestorage.c b/src/mainboard/google/brya/variants/taeko/runtimestorage.c
new file mode 100644
index 0000000..3f470d5
--- /dev/null
+++ b/src/mainboard/google/brya/variants/taeko/runtimestorage.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <soc/romstage.h>
+#include <fw_config.h>
+#include <gpio.h>
+#include <console/console.h>
+#include <baseboard/variants.h>
+#include <soc/pcie.h>
+
+void pcieclk_override(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+	printk(BIOS_INFO, "Kevin_Say hello.\n");
+	printk(BIOS_INFO, "Kevin_GPIOF19: %x.\n", gpio_get(GPP_F19));
+	if(fw_config_probe(FW_CONFIG(BOOT_NVME_MASK, BOOT_NVME_ENABLED)) && 
+	    fw_config_probe(FW_CONFIG(BOOT_EMMC_MASK, BOOT_EMMC_ENABLED))){
+		printk(BIOS_INFO, "Kevin_7035.\n");
+		const struct pad_config *pads;
+		size_t pads_num;
+
+		pads = variant_special_gpio_table(&pads_num);
+		gpio_configure_pads(pads, pads_num);
+		
+		if(!gpio_get(GPP_F19)){
+			m_cfg->PcieClkSrcUsage[0] = 8;
+			m_cfg->PcieClkSrcClkReq[0] = 0;
+		}
+	}
+}