Attention is currently required from: Jason Glenesk, Raul Rangel.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59591 )
Change subject: soc/amd/common/block/include/gpio_defs: drop 8k pullup define
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59591/comment/f3df8f87_a726790f
PS1, Line 9: reserved in all SoCs
turns out that version 3.14 of #55570 had this bit defined, but version 3.16 and 3. […]
the Cezanne PPR has reset values for that bit and it's 0, so this patch shouldn't change the value that will end up in that register at bit 19. the other PPRs/BKDGs only listed the bit as reserved with no reset value being specified
--
To view, visit
https://review.coreboot.org/c/coreboot/+/59591
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33
Gerrit-Change-Number: 59591
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held
felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson
marshalldawson3rd@gmail.com
Gerrit-Reviewer: Raul Rangel
rrangel@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Attention: Jason Glenesk
jason.glenesk@gmail.com
Gerrit-Attention: Raul Rangel
rrangel@chromium.org
Gerrit-Comment-Date: Wed, 24 Nov 2021 18:00:34 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Marshall Dawson
marshalldawson3rd@gmail.com
Comment-In-Reply-To: Felix Held
felix-coreboot@felixheld.de
Gerrit-MessageType: comment