Change in ...coreboot[master]: soc/intel/cannonlake: Move power_state functions to pmutil.c
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31787
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
soc/intel/cannonlake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938 BRANCH=none TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/Makefile.inc D src/soc/intel/cannonlake/romstage/power_state.c 3 files changed, 64 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31787/1
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7d6ee65..4e1500f 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -198,3 +198,67 @@ { return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); } + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_b & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index c3bfdbb..75d7985 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -13,7 +13,6 @@ # GNU General Public License for more details. #
-romstage-y += power_state.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c deleted file mode 100644 index 9137507..0000000 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <console/console.h> -#include <device/device.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/tco.h> -#include <string.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> - -static inline int deep_s3_enabled(void) -{ - uint32_t deep_s3_pol; - - deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); - return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); -} - -/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) -{ - - /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = ACPI_S5; - - /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. - */ - if (prev_sleep_state == ACPI_S3) { - /* PWR_FLR represents deep sleep power well loss. */ - uint32_t mask = PWR_FLR; - - /* If deep s3 isn't enabled check the suspend well too. */ - if (!deep_s3_enabled()) - mask |= SUS_PWR_FLR; - - if (ps->gen_pmcon_b & mask) - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -void soc_fill_power_state(struct chipset_power_state *ps) -{ - uint8_t *pmc; - - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); - - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); - - pmc = pmc_mmio_regs(); - ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); - ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); - ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); - ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); - - printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", - ps->gblrst_cause[0], ps->gblrst_cause[1]); -}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 1:
(68 comments)
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 204: uint32_t deep_s3_pol; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 204: uint32_t deep_s3_pol; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 206: deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 206: deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 207: return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 207: return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 212: int prev_sleep_state) code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 212: int prev_sleep_state) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 215: /* code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 216: * Check for any power failure to determine if this a wake from code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 217: * S5 because the PCH does not set the WAK_STS bit when waking code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 218: * from a true G3 state. code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@21... PS1, Line 219: */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 220: if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 220: if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 221: prev_sleep_state = ACPI_S5; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 221: prev_sleep_state = ACPI_S5; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 223: /* code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 224: * If waking from S3 determine if deep S3 is enabled. If not, code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 225: * need to check both deep sleep well and normal suspend well. code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 226: * Otherwise just check deep sleep well. code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 227: */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 228: if (prev_sleep_state == ACPI_S3) { code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 228: if (prev_sleep_state == ACPI_S3) { please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@22... PS1, Line 229: /* PWR_FLR represents deep sleep power well loss. */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 230: uint32_t mask = PWR_FLR; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 230: uint32_t mask = PWR_FLR; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 232: /* If deep s3 isn't enabled check the suspend well too. */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 233: if (!deep_s3_enabled()) code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 233: if (!deep_s3_enabled()) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 234: mask |= SUS_PWR_FLR; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 234: mask |= SUS_PWR_FLR; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 236: if (ps->gen_pmcon_b & mask) code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 236: if (ps->gen_pmcon_b & mask) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 237: prev_sleep_state = ACPI_S5; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 237: prev_sleep_state = ACPI_S5; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 238: } code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@23... PS1, Line 238: } please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 240: return prev_sleep_state; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 240: return prev_sleep_state; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 245: uint8_t *pmc; code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 245: uint8_t *pmc; please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 247: ps->tco1_sts = tco_read_reg(TCO1_STS); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 247: ps->tco1_sts = tco_read_reg(TCO1_STS); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 248: ps->tco2_sts = tco_read_reg(TCO2_STS); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@24... PS1, Line 248: ps->tco2_sts = tco_read_reg(TCO2_STS); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 250: printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 250: printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 251: ps->tco1_sts, ps->tco2_sts); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 251: ps->tco1_sts, ps->tco2_sts); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 253: pmc = pmc_mmio_regs(); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 253: pmc = pmc_mmio_regs(); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 254: ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 254: ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 255: ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 255: ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 256: ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 256: ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 257: ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 257: ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 259: printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@25... PS1, Line 259: printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 260: ps->gen_pmcon_a, ps->gen_pmcon_b); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 260: ps->gen_pmcon_a, ps->gen_pmcon_b); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 262: printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 262: printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", please, no spaces at the start of a line
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 263: ps->gblrst_cause[0], ps->gblrst_cause[1]); code indent should use tabs where possible
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@26... PS1, Line 263: ps->gblrst_cause[0], ps->gblrst_cause[1]); please, no spaces at the start of a line
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31787
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
soc/intel/cannonlake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938 BRANCH=none TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/Makefile.inc D src/soc/intel/cannonlake/romstage/power_state.c 3 files changed, 64 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31787/2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 204: uint32_t deep_s3_pol;
code indent should use tabs where possible
Done
https://review.coreboot.org/#/c/31787/1/src/soc/intel/cannonlake/pmutil.c@20... PS1, Line 204: uint32_t deep_s3_pol;
please, no spaces at the start of a line
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG@10 PS2, Line 10: It allows the functions to be used across romstage and smm. : Can this not be achieved by just adding power_state.c to smm stage?
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG@10 PS2, Line 10: It allows the functions to be used across romstage and smm. :
Can this not be achieved by just adding power_state. […]
Yes, that will also work but since power_state.c was residing inside romstage specific folder and if i had to include power_state.c to smm stage, then i had to include it inside the romstage Makefile. Instead i thought of moving it outside the romstage folder so that i need not include smm stage inside romstage specific folder.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31787/2//COMMIT_MSG@10 PS2, Line 10: It allows the functions to be used across romstage and smm. :
Yes, that will also work but since power_state. […]
Aah okay.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31787 )
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c ......................................................................
soc/intel/cannonlake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938 BRANCH=none TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36 Signed-off-by: V Sowmya v.sowmya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/Makefile.inc D src/soc/intel/cannonlake/romstage/power_state.c 3 files changed, 64 insertions(+), 89 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7d6ee65..16c4db6 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -198,3 +198,67 @@ { return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); } + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_b & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->tco1_sts = tco_read_reg(TCO1_STS); + ps->tco2_sts = tco_read_reg(TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc index c3bfdbb..75d7985 100644 --- a/src/soc/intel/cannonlake/romstage/Makefile.inc +++ b/src/soc/intel/cannonlake/romstage/Makefile.inc @@ -13,7 +13,6 @@ # GNU General Public License for more details. #
-romstage-y += power_state.c romstage-y += romstage.c romstage-y += fsp_params.c romstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c deleted file mode 100644 index 9137507..0000000 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <console/console.h> -#include <device/device.h> -#include <intelblocks/pmclib.h> -#include <intelblocks/tco.h> -#include <string.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> - -static inline int deep_s3_enabled(void) -{ - uint32_t deep_s3_pol; - - deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); - return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); -} - -/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) -{ - - /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) - prev_sleep_state = ACPI_S5; - - /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. - */ - if (prev_sleep_state == ACPI_S3) { - /* PWR_FLR represents deep sleep power well loss. */ - uint32_t mask = PWR_FLR; - - /* If deep s3 isn't enabled check the suspend well too. */ - if (!deep_s3_enabled()) - mask |= SUS_PWR_FLR; - - if (ps->gen_pmcon_b & mask) - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -void soc_fill_power_state(struct chipset_power_state *ps) -{ - uint8_t *pmc; - - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); - - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); - - pmc = pmc_mmio_regs(); - ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); - ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); - ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); - ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); - - printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", - ps->gblrst_cause[0], ps->gblrst_cause[1]); -}
-
build bot (Jenkins) (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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V Sowmya (Code Review)