Attention is currently required from: Marshall Dawson, Name of user not set #1003801, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58279 )
Change subject: src/soc/amd/cezanne: enable clock gating ......................................................................
Patch Set 2:
(2 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/58279/comment/68bc88fa_9add0c26 PS1, Line 178: t |= ALINKCLK_GATEOFFEN; : t |= BLINKCLK_GATEOFFEN;
since we're setting these two bits, we should also explicitly set ISACONTROL[abclkgateen]
Done
File src/soc/amd/cezanne/include/soc/southbridge.h:
https://review.coreboot.org/c/coreboot/+/58279/comment/61410bd2_ca61e0ce PS1, Line 113: #define MISC_CLKGATEDCNTL 0x2c : #define ALINKCLK_GATEOFFEN BIT(16) : #define BLINKCLK_GATEOFFEN BIT(17) : #define XTAL_PAD_S3_TURNOFF_EN BIT(20) : #define XTAL_PAD_S5_TURNOFF_EN BIT(21) : #define MISC_CGPLL_CONFIGURATION0 0x30 : #define USB_PHY_CMCLK_S3_DIS BIT(8) : #define USB_PHY_CMCLK_S0I3_DIS BIT(9) : #define USB_PHY_CMCLK_S5_DIS BIT(10)
would be good to move those register and bit definitions so that the registers are ordered; so this […]
Done