[M] Change in coreboot[master]: sb/intel/common: Fix GPE0 related register conflict

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69669 )

Change subject: sb/intel/common: Fix GPE0 related register conflict
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Patch Set 1:

(2 comments)

File src/southbridge/intel/common/pmutil.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163740):
https://review.coreboot.org/c/coreboot/+/69669/comment/9c182006_9f3df322 
PS1, Line 76: 	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
trailing statements should be on next line

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163740):
https://review.coreboot.org/c/coreboot/+/69669/comment/c54fb1c6_e945d35e 
PS1, Line 134: 	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97/USB5 ");
trailing statements should be on next line