Change in coreboot[master]: soc/rockchip/rk3399/sdram: Add phy_ctrl_reset

[Moritz Fischer (Code Review)]

Attention is currently required from: Julius Werner.
Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50890 )

Change subject: soc/rockchip/rk3399/sdram: Add phy_ctrl_reset
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soc/rockchip/rk3399/sdram: Add phy_ctrl_reset

Add support phy pctrl reset for both channel 0 and 1.

Signed-off-by: Moritz Fischer 
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
---
M src/soc/rockchip/rk3399/sdram.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/50890/1

diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 194197a..c0a0497 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -100,6 +100,18 @@
    }
 }

+static void phy_pctrl_reset(u32 channel)
+{
+	rkclk_ddr_reset(channel, 1, 1);
+	udelay(10);
+
+	rkclk_ddr_reset(channel, 1, 0);
+	udelay(10);
+
+	rkclk_ddr_reset(channel, 0, 0);
+	udelay(10);
+}
+
 static void phy_dll_bypass_set(u32 channel,
    struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
 {
@@ -1103,6 +1115,7 @@
    rkclk_configure_ddr(ddr_freq);

for (channel = 0; channel < 2; channel++) {
+		phy_pctrl_reset(channel);
    	phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq);

if (channel >= params->num_channels)