Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL

[Sridhar Siricilla (Code Review)]

Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62987

to look at the new patch set (#4).

Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL
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soc/intel/alderlake: Log CSE RO write protection info for ADL

The patch logs write protection information for Alder Lake platform.
As part of write protection informaiton, coreboot logs status on CSE RO
write protection and range. Also, triggers assert if EOM is disabled,
and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
    [DEBUG]  ME: WP for RO is enabled        : YES
    [DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla 
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
---
M src/soc/intel/alderlake/me.c
1 file changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/4