Change in coreboot[master]: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59852 )

Change subject: soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h
......................................................................

soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h

This enum is useful to have around for more than just the one file, so
move it to a common header file, and while we're there, also add an
option for UNKNOWN.

TEST=boot test on brya0

Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 11 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59852/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 121251e..d319abb 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -23,11 +23,6 @@

#define CPU_PCIE_BASE			0x40

-enum pcie_rp_type {
-	PCH_PCIE_RP,
-	CPU_PCIE_RP,
-};
-
 enum vtd_base_index_type {
    VTD_GFX,
    VTD_IPU,
@@ -40,11 +35,11 @@

static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
 {
-	assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP);
+	assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU);

-	if (type == PCH_PCIE_RP)
+	if (type == PCIE_RP_PCH)
    	return rp_number;
-	else // type == CPU_PCIE_RP
+	else // type == PCIE_RP_CPU
    	return CPU_PCIE_BASE + rp_number;
 }

@@ -82,12 +77,12 @@

/* Configure PCH PCIE ports */
    m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
-	pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp,
+	pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp,
    		CONFIG_MAX_PCH_ROOT_PORTS);

/* Configure CPU PCIE ports */
    m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
-	pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp,
+	pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp,
    		CONFIG_MAX_CPU_ROOT_PORTS);
 }

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 8ed3e3d..f74706e 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -111,4 +111,10 @@
  */
 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);

+enum pcie_rp_type {
+	PCIE_RP_UNKNOWN,
+	PCIE_RP_CPU,
+	PCIE_RP_PCH,
+};
+
 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */