New patch to review for coreboot: ed62520 Intel 945, 5000 Sandy Bridge: Unify `udelay.c`
Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220
-gerrit
commit ed625200b37bc66d1ad893d3edc174f944f946e2 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Wed May 8 17:08:55 2013 +0200
Intel 945, 5000 Sandy Bridge: Unify `udelay.c`
1. Add secunet’s copyright as this was added for the function `multiply_to_tsc()`. 2. Change the comparison from < to <= as done for Sandy Bridge. 3. i5000: Remove `tsc = rdtsc();` which is executed in the do-while-loop too. 4. Use the same indentation and comment placement. (Run `indent -linux …` too.) 5. Use the same spelling of words.
Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/northbridge/intel/i5000/udelay.c | 12 ++++++------ src/northbridge/intel/i945/udelay.c | 13 +++++++------ src/northbridge/intel/sandybridge/udelay.c | 17 +++++++++-------- 3 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 699e0d4..d081acc 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -24,7 +24,9 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h>
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ static inline void multiply_to_tsc(tsc_t * const tsc, const u32 a, const u32 b) { tsc->lo = (a & 0xffff) * (b & 0xffff); @@ -36,7 +38,7 @@ static inline void multiply_to_tsc(tsc_t * const tsc, const u32 a, const u32 b) }
/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */
void udelay(u32 us) @@ -75,7 +77,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f;
- d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);
@@ -87,10 +89,8 @@ void udelay(u32 us) tsc1.lo = dword; tsc1.hi += tscd.hi;
- tsc = rdtsc(); - do { tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); + || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); } diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 780c730..d081acc 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,8 +24,10 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h>
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ +static inline void multiply_to_tsc(tsc_t * const tsc, const u32 a, const u32 b) { tsc->lo = (a & 0xffff) * (b & 0xffff); tsc->hi = ((tsc->lo >> 16) @@ -36,7 +38,7 @@ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) }
/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */
void udelay(u32 us) @@ -75,7 +77,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f;
- d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);
@@ -90,6 +92,5 @@ void udelay(u32 us) do { tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - + || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d..10b4f7b 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,23 +23,23 @@ #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h>
-/** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz - */ - /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. * This code is used to prevent use of libgcc's umoddi3. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +static inline void multiply_to_tsc(tsc_t * const tsc, const u32 a, const u32 b) { tsc->lo = (a & 0xffff) * (b & 0xffff); tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); }
+/** + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz + */ + void udelay(u32 us) { u32 dword; @@ -50,7 +51,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff;
- d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
-
Paul Menzel