Evan Green has uploaded this change for review. ( https://review.coreboot.org/25643
Change subject: cheza: Fix SPI clocking and pinmuxing ......................................................................
cheza: Fix SPI clocking and pinmuxing
The original SDM845 SPI code in question clocked the SPI bus at 200MHz. The Winbond part can only go up to 104MHz. This change clocks it at 100MHz, which still leaves a little bit of headroom for variations. It also removes the extra data[2] and data[3] pinmuxing, as this board does not use quad SPI.
BUG=b:74020650 TEST=Booting via SPI on Cheza now works
Change-Id: I0c1432d4e31fa07b192d914c987327ae4e2ed11f --- M src/soc/qualcomm/sdm845/fs_spi.c 1 file changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/25643/1
diff --git a/src/soc/qualcomm/sdm845/fs_spi.c b/src/soc/qualcomm/sdm845/fs_spi.c index 0199c5b..0197773 100644 --- a/src/soc/qualcomm/sdm845/fs_spi.c +++ b/src/soc/qualcomm/sdm845/fs_spi.c @@ -380,8 +380,8 @@
*(volatile uint32_t *)(gcc_qspi_base + AHB_CBCR) = 0x00000001; *(volatile uint32_t *)(gcc_qspi_base + SER_CBCR) = 0x00000001; - // 200MHZ - *(volatile uint32_t *)(gcc_qspi_base + SER_CFG_RCGR) = 0x00000105; + // 1200MHz / 12 = 100MHZ + *(volatile uint32_t *)(gcc_qspi_base + SER_CFG_RCGR) = 0x0000010B; // ROOT_EN and UPDATE *(volatile uint32_t *)(gcc_qspi_base + SER_CMD_RCGR) = 0x00000003; return true; @@ -433,10 +433,6 @@ *(volatile uint32_t *)(tlmm_base + 0x1000 * 91) = 0x0011; // qspi_data[1] (2ma, fcn 4, PD) *(volatile uint32_t *)(tlmm_base + 0x1000 * 92) = 0x0011; - // qspi_data[2] (2ma, fcn 4, PD) - *(volatile uint32_t *)(tlmm_base + 0x1000 * 93) = 0x0011; - // qspi_data[3] (2ma, fcn 4, PD) - *(volatile uint32_t *)(tlmm_base + 0x1000 * 94) = 0x0011; return true; }