Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49523 )
Change subject: northbridge/intel/x4x/dq_dqs.c: Remove repeated word ......................................................................
northbridge/intel/x4x/dq_dqs.c: Remove repeated word
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/x4x/dq_dqs.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/49523/1
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 82dca44..4722dfe 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -746,7 +746,7 @@ * DDR3 uses flyby topology where the clock signal takes a different path * than the data signal, to allow for better signal intergrity. * Therefore the delay on the data signals needs to account for this. - * This is done by by sampleling the the DQS write (tx) signal back over + * This is done by sampleling the DQS write (tx) signal back over * the DQ signal and looking for delay values where the sample transitions * from high to low. * Here the following is done: