[L] Change in coreboot[main]: superio/ite/common: Add common driver for GPIO and LED configuration
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83355?usp=email )
Change subject: superio/ite/common: Add common driver for GPIO and LED configuration ......................................................................
superio/ite/common: Add common driver for GPIO and LED configuration
Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The driver supports most ITE SuperIOs, except Embedded Controllers. The driver allows configuring every GPIO property with pin granularity.
The patch: - adds a new GPIO driver in the ite/common directory - enables the driver for ITE SIOs supporting the GPIO register layout (confirmed with datasheets for the modified ITE SIO Kconfigs). Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM and must then provide the number of GPIO sets specific to a chip via SUPERIO_ITE_COMMON_NUM_GPIO_SETS. - Removes the custom IT8772F GPIO helpers - Refactors the mainboards' code to use the new driver where possible
Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/jecht/led.c M src/mainboard/hp/pro_3500_series/led.c M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c M src/superio/ite/Makefile.mk M src/superio/ite/common/Kconfig A src/superio/ite/common/gpio.c A src/superio/ite/common/ite_gpio.h M src/superio/ite/it8613e/Kconfig M src/superio/ite/it8659e/Kconfig M src/superio/ite/it8659e/it8659e.h M src/superio/ite/it8712f/Kconfig M src/superio/ite/it8718f/Kconfig M src/superio/ite/it8720f/Kconfig M src/superio/ite/it8721f/Kconfig M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8772f/Makefile.mk D src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8783ef/Kconfig M src/superio/ite/it8784e/Kconfig M src/superio/ite/it8786e/Kconfig 25 files changed, 515 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83355/1
diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index da5002f..c15657b 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,17 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h"
void set_power_led(int state) { - it8772f_gpio_led(IT8772F_GPIO_DEV, - 1, /* set */ - 0x01, /* select */ - state == LED_BLINK ? 0x01 : 0x00, /* polarity */ - state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ - 0x01, /* output */ - state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ - SIO_GPIO_BLINK_GPIO10, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO10 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, IT8772F_GPIO_REG_SELECT(0), 0x01); + ite_gpio_setup(IT8772F_GPIO_DEV, 10, + state == LED_BLINK ? ITE_GPIO_POL_INVERT : ITE_GPIO_POL_NO_INVERT, + state == LED_BLINK ? ITE_GPIO_PULLUP_EN : ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 10, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); } diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index 49d7918..6e75c51 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,17 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h"
void set_power_led(int state) { - it8772f_gpio_led(IT8772F_GPIO_DEV, - 2, /* set */ - 0xF7, /* select */ - state == LED_OFF ? 0x00 : 0x04, /* polarity */ - state == LED_BLINK ? 0x04 : 0x00, /* pullup/pulldown */ - 0x04, /* output */ - state == LED_BLINK ? 0x00 : 0x04, /* I/O function */ - SIO_GPIO_BLINK_GPIO22, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO22 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, IT8772F_GPIO_REG_SELECT(1), 0xf7); + ite_gpio_setup(IT8772F_GPIO_DEV, 22, + state == LED_OFF ? ITE_GPIO_POL_NO_INVERT : ITE_GPIO_POL_INVERT, + state == LED_BLINK ? ITE_GPIO_PULLUP_EN : ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 22, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); } diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 8a6a304..c9734bc 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "onboard.h"
@@ -8,18 +10,21 @@ int polarity;
if (CONFIG(BOARD_GOOGLE_TIDUS)) { - polarity = state == LED_OFF ? 0x00 : 0x01; + polarity = state == LED_OFF ? ITE_GPIO_POL_NO_INVERT : ITE_GPIO_POL_INVERT; } else { - polarity = state == LED_BLINK ? 0x01 : 0x00; + polarity = state == LED_BLINK ? ITE_GPIO_POL_INVERT : ITE_GPIO_POL_NO_INVERT; }
- it8772f_gpio_led(IT8772F_GPIO_DEV, - 1, /* set */ - 0x01, /* select */ - polarity, /* polarity */ - state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ - 0x01, /* output */ - state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ - SIO_GPIO_BLINK_GPIO10, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO10 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, IT8772F_GPIO_REG_SELECT(0), 0x01); + ite_gpio_setup(IT8772F_GPIO_DEV, 10, + polarity, + state == LED_BLINK ? ITE_GPIO_PULLUP_EN : ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 10, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); } diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3500_series/led.c index 073f5f5..1978d32 100644 --- a/src/mainboard/hp/pro_3500_series/led.c +++ b/src/mainboard/hp/pro_3500_series/led.c @@ -1,17 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> + #include "common_defines.h" #include "led.h"
void set_power_led(int state) { - // Board has a dual color LED - it8772f_gpio_setup( - GPIO_DEV, - 2, /* set */ - 0xf3 | LED_BOTH, /* select, 0xf3 is default */ - state, /* polarity */ - 0x00, /* pullup */ - LED_BOTH, /* output */ - 0x00); /* enable */ + // Board has a dual color LED: GPIO22 and GPIO23 + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(1), 0xf3 | LED_BOTH); + ite_gpio_setup(GPIO_DEV, 22, + state & LED_WHITE ? ITE_GPIO_POL_INVERT : ITE_GPIO_POL_NO_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_ALT_FN_MODE); + ite_gpio_setup(GPIO_DEV, 23, + state & LED_YELLOW ? ITE_GPIO_POL_INVERT : ITE_GPIO_POL_NO_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_ALT_FN_MODE); } diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 852759e..b048c91 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -5,6 +5,7 @@ #include <pc80/mc146818rtc.h> #include <bootmode.h> #include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> @@ -58,32 +59,64 @@ * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(GPIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); - + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(0), 0x05); + ite_gpio_setup(GPIO_DEV, 10, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup(GPIO_DEV, 12, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(GPIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); - + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(1), 0x04); + ite_gpio_setup(GPIO_DEV, 22, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(GPIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); - + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(2), 0x04); + ite_gpio_setup(GPIO_DEV, 32, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); /* * GPIO45 as LED_POWER# */ - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, - (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20); + ite_gpio_setup(GPIO_DEV, 45, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_EN, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); /* * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(GPIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(GPIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(4), 0x06); + ite_gpio_setup(GPIO_DEV, 51, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup(GPIO_DEV, 52, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); }
void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index f9b9d3b..b1878f8 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -8,6 +8,8 @@ #include <northbridge/intel/sandybridge/sandybridge.h>
/* Include for SIO helper functions */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
@@ -20,17 +22,31 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, - (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */ - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20); + ite_gpio_setup(GPIO_DEV, 45, + ITE_GPIO_POL_INVERT, + ITE_GPIO_PULLUP_EN, + ITE_GPIO_OUTPUT, + ITE_GPIO_ALT_FN_MODE); + ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); break;
case ACPI_S5: - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, - (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20); + ite_gpio_setup(GPIO_DEV, 45, + ITE_GPIO_POL_NO_INVERT, + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_OUTPUT, + ITE_GPIO_SIMPLE_IO_MODE); + ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_FREQ_1HZ); break; default: break; diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk index 678ea95..afbce8a 100644 --- a/src/superio/ite/Makefile.mk +++ b/src/superio/ite/Makefile.mk @@ -4,11 +4,15 @@ bootblock-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c
+bootblock-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c +romstage-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c + ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
## include generic ite driver to smm to control S3-relevant functions smm-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c +smm-$(CONFIG_SUPERIO_ITE_COMMON_GPIO_PRE_RAM) += common/gpio.c
subdirs-y += it8528e subdirs-y += it8613e diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 4701056..c5eeec6 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -5,6 +5,33 @@ config SUPERIO_ITE_COMMON_PRE_RAM bool
+config SUPERIO_ITE_COMMON_GPIO_PRE_RAM + bool + help + Enable generic pre-ram driver for configuring ITE SIO GPIOs. + It applies only to ITE SIOs not ITE ECs using LDN 7 (typically) + to configure GPIO Simple I/O mode. + +if SUPERIO_ITE_COMMON_GPIO_PRE_RAM + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + int + help + The maximum number of GPIO sets supported by ITE SIO chip. + Each SIO chip must set this config option to a proper values + if it intends to enable SUPERIO_ITE_COMMON_GPIO_PRE_RAM. + +config SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT + bool + default n + help + Selected ITE SIOs control the GPIO LED frequency using 5 bits + instead of two. The LED register layout is also different for + these chips. Select this if the SIO GP LED Frequency control + field has 5 bits and support duty cycle as well. + +endif + # Generic ITE environment controller driver config SUPERIO_ITE_ENV_CTRL bool diff --git a/src/superio/ite/common/gpio.c b/src/superio/ite/common/gpio.c new file mode 100644 index 0000000..c04cf00 --- /dev/null +++ b/src/superio/ite/common/gpio.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "ite.h" +#include "ite_gpio.h" + +/* Catch ITE SIOs that enable the driver but do not configure the number of sets */ +#if CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS == 0 +#error "Maximum number of ITE SIO GPIO sets not provided" +#endif + +#if CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS > 10 +#error "This ITE SIO GPIO driver support up to 10 GPIO sets" +#endif + +/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ +#define GPIO_REG_POLARITY(x) \ + (((x) > 8) ? (0xd1 + ((x) - 9) * 5) \ + : (0xb0 + ((x) - 1)) \ + ) + +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ +#define GPIO_REG_PULLUP(x) \ + (((x) > 8) ? (0xd4 + ((x) - 9) * 5) \ + : (0xb8 + ((x) - 1)) \ + ) + +/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ +#define GPIO_REG_FN_SELECT(x) \ + (((x) > 8) ? (0xd3 + ((x) - 9) * 5) \ + : (0xc0 + ((x) - 1)) \ + ) + +/* GPIO Mode: 0: input mode, 1: output mode */ +#define GPIO_REG_OUTPUT(x) \ + (((x) > 8) ? (0xd2 + ((x) - 9) * 5) \ + : (0xc8 + ((x) - 1)) \ + ) + +/* GPIO LED pin mapping register */ +#define GPIO_REG_LED_PINMAP(x) (0xf8 + ((x) & 1) * 2) +#define GPIO_LED_PIN_LOC(set, pin) ((((set) & 7) << 3) | ((pin) & 7)) +#define GPIO_LED_PIN_LOC_MASK 0x3f +/* GPIO LED control register */ +#define GPIO_REG_LED_CONTROL(x) (0xf9 + ((x) & 1) * 2) +#define GPIO_LED_OUTPUT_LOW(x) (((x) & 1) << 0) +#define GPIO_LED_PINMAP_CLEAR(x) (((x) & 1) << 4) +#define GPIO_LED_SHORT_LOW_PULSE(x) \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) ? (((x) & 1) << 5) \ + : (((x) & 1) << 3) \ + ) +#define GPIO_LED_FREQ_SEL(x) \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) \ + ? ((((x) & 0x18) << 3) | (((x) & 0x7) << 1)) \ + : (((x) & 0x3) << 1) \ + ) +#define GPIO_LED_FREQ_SEL_MASK \ + (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT) ? 0xce : 0x06) + +static bool ite_has_gpio_fn_select_reg(u8 set) +{ + /* IT8718F has all registers for all sets. */ + if (CONFIG(SUPERIO_ITE_IT8718F)) + return true; + + /* Typically ITE GPIO sets 6 to 8 don't have enable and polarity registers. */ + if (set < 6 || set > 8) + return true; + + return false; +} + +static bool ite_has_gpio_polarity_reg(u8 set) +{ + /* IT8718F has all registers for all sets. */ + if (CONFIG(SUPERIO_ITE_IT8718F)) + return true; + + /* IT8720F/IT8721F has polarity register for all GPIO sets */ + if (CONFIG(SUPERIO_ITE_IT8720F) || CONFIG(SUPERIO_ITE_IT8721F)) + return true; + + /* Typically ITE GPIO sets 6 to 8 don't have enable and polarity registers. */ + if (set < 6 || set > 8) + return true; + + return false; +} + +/* + * Configures a single GPIO given its number as gpio_num and properties, such + * as polarity, pull and direction ("output" parameter). The "enable" + * parameter can configure the GPIO in Simple I/O mode when set or Alternate + * function mode when clear. Some chips may also not support configuring all + * properties for a particular GPIO. It is left to the implementer to check if + * GPIO settings are valid for given gpio_num. + */ +void ite_gpio_setup(pnp_devfn_t gpiodev, u8 gpio_num, enum ite_gpio_polarity polarity, + enum ite_gpio_pullup pullup, enum ite_gpio_direction output, + enum ite_gpio_mode enable) +{ + u8 set = (gpio_num / 10); + u8 pin = (gpio_num % 10); + + /* Number of configurable sets is chip dependent, 8 pins each */ + if (gpio_num < 10 || set > CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS || pin > 7) + return; + + pnp_enter_conf_state(gpiodev); + pnp_set_logical_device(gpiodev); + + if (ite_has_gpio_fn_select_reg(set)) + pnp_unset_and_set_config(gpiodev, GPIO_REG_FN_SELECT(set), + 1 << pin, enable << pin); + + if (ite_has_gpio_polarity_reg(set)) + pnp_unset_and_set_config(gpiodev, GPIO_REG_POLARITY(set), + 1 << pin, polarity << pin); + + + pnp_unset_and_set_config(gpiodev, GPIO_REG_OUTPUT(set), 1 << pin, output << pin); + + /* + * ITE GPIO Sets 7 and 8 don't have a pullup register. + * See IT8786/IT8625 datasheet section 8.10.10. + * Also applies to IT8728F. + */ + if (set != 7 && set != 8) + pnp_unset_and_set_config(gpiodev, GPIO_REG_PULLUP(set), 1 << pin, pullup << pin); + + pnp_exit_conf_state(gpiodev); +} + +void ite_gpio_setup_led(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_led led_no, + enum ite_led_short_pulse short_low_pulse, + enum ite_led_pinmap_clear pin_map_clear, + enum ite_led_output_low output_low, + enum ite_led_frequency freq) +{ + u8 set = (gpio_num / 10); + u8 pin = (gpio_num % 10); + u8 reg = 0; + + /* Number of configurable sets is chip dependent, 8 pins each */ + if (gpio_num < 10 || set > CONFIG_SUPERIO_ITE_COMMON_NUM_GPIO_SETS || pin > 7) + return; + + /* LED is available only for GPIO sets 1-5 */ + if (set > 5) + return; + + pnp_enter_conf_state(gpiodev); + pnp_set_logical_device(gpiodev); + + /* Pinmap clear bit is only available when frequency is controlled with 5 bits */ + if (CONFIG(SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT)) + reg |= GPIO_LED_PINMAP_CLEAR(pin_map_clear); + + reg |= GPIO_LED_OUTPUT_LOW(output_low); + reg |= GPIO_LED_SHORT_LOW_PULSE(short_low_pulse); + reg |= GPIO_LED_FREQ_SEL(freq); + pnp_write_config(gpiodev, GPIO_REG_LED_CONTROL(led_no), reg); + + reg = GPIO_LED_PIN_LOC(set, pin); + pnp_write_config(gpiodev, GPIO_REG_LED_PINMAP(led_no), reg); + + pnp_exit_conf_state(gpiodev); +} diff --git a/src/superio/ite/common/ite_gpio.h b/src/superio/ite/common/ite_gpio.h new file mode 100644 index 0000000..6383648 --- /dev/null +++ b/src/superio/ite/common/ite_gpio.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_COMMON_GPIO_PRE_RAM_H +#define SUPERIO_ITE_COMMON_GPIO_PRE_RAM_H + +#include <device/pnp_type.h> +#include <stdint.h> + +enum ite_gpio_polarity { + ITE_GPIO_POL_NO_INVERT, + ITE_GPIO_POL_INVERT +}; + +enum ite_gpio_pullup { + ITE_GPIO_PULLUP_DIS, + ITE_GPIO_PULLUP_EN +}; + +enum ite_gpio_direction { + ITE_GPIO_INPUT, + ITE_GPIO_OUTPUT +}; + +enum ite_gpio_mode { + ITE_GPIO_ALT_FN_MODE, + ITE_GPIO_SIMPLE_IO_MODE +}; + +enum ite_gpio_led { + ITE_GPIO_LED_1, + ITE_GPIO_LED_2 +}; + +enum ite_led_short_pulse { + ITE_LED_SHORT_PULSE_DISABLE, + ITE_LED_SHORT_PULSE_ENABLE +}; + +enum ite_led_output_low { + ITE_LED_OUTPUT_LOW_DISABLE, + ITE_LED_OUTPUT_LOW_ENABLE +}; + +/* + * Only for ITE SIOs with 5-bit frequency selection. + * When enabled, the LED pin mapping register is cleared when PANSWH# is low for over 4s. + */ +enum ite_led_pinmap_clear { + ITE_LED_PINMAP_CLEAR_DISABLE, + ITE_LED_PINMAP_CLEAR_ENABLE +}; + +enum ite_led_frequency { + /* Most ITE SIOs have 2-bit frequency selection */ + ITE_LED_FREQ_4HZ = 0, + ITE_LED_FREQ_1HZ = 1, + ITE_LED_FREQ_0P25HZ = 2, + ITE_LED_FREQ_0P125Hz = 3, + /* ITE SIOs with 5-bit frequency selection: IT8625, IT8613 */ + ITE_LED_FREQ_4HZ_DUTY_50 = 0, + ITE_LED_FREQ_1HZ_DUTY_50 = 1, + ITE_LED_FREQ_0P25HZ_DUTY_50 = 2, + ITE_LED_FREQ_2Hz_DUTY_50 = 3, + ITE_LED_FREQ_0P25HZ_DUTY_25 = 4, + ITE_LED_FREQ_0P25HZ_DUTY_75 = 5, + ITE_LED_FREQ_0P125HZ_DUTY_25 = 6, + ITE_LED_FREQ_0P125Hz_DUTY_75 = 7, + ITE_LED_FREQ_0P4Hz_DUTY_20 = 8, + ITE_LED_FREQ_0P5Hz_DUTY_50 = 16, + ITE_LED_FREQ_0P125Hz_DUTY_50 = 24, +}; + + +void ite_gpio_setup(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_polarity polarity, + enum ite_gpio_pullup pullup, + enum ite_gpio_direction output, + enum ite_gpio_mode enable); + +void ite_gpio_setup_led(pnp_devfn_t gpiodev, u8 gpio_num, + enum ite_gpio_led led_no, + enum ite_led_short_pulse short_low_pulse, + enum ite_led_pinmap_clear pin_map_clear, + enum ite_led_output_low output_low, + enum ite_led_frequency freq); + + +#endif /* SUPERIO_ITE_COMMON_PRE_RAM_H */ diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..cc709ae 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -3,9 +3,18 @@ config SUPERIO_ITE_IT8613E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8613E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8659e/Kconfig b/src/superio/ite/it8659e/Kconfig index 92ee4c1..43b8c95 100644 --- a/src/superio/ite/it8659e/Kconfig +++ b/src/superio/ite/it8659e/Kconfig @@ -3,8 +3,17 @@ config SUPERIO_ITE_IT8659E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + + +if SUPERIO_ITE_IT8659E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8659e/it8659e.h b/src/superio/ite/it8659e/it8659e.h index 4fa91e9..f6eda07 100644 --- a/src/superio/ite/it8659e/it8659e.h +++ b/src/superio/ite/it8659e/it8659e.h @@ -11,24 +11,4 @@ #define IT8659E_GPIO 0x07 /* GPIO */ #define IT8659E_CIR 0x0A /* CIR */
-/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ -#define GPIO_REG_POLARITY(x) (0xb0 + (x)) -#define GPIO_POL_NO_INVERT 0 -#define GPIO_POL_INVERT 1 - -/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ -#define GPIO_REG_PULLUP(x) (0xb8 + (x)) -#define GPIO_PULLUP_DIS 0 -#define GPIO_PULLUP_EN 1 - -/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ -#define GPIO_REG_ENABLE(x) (0xc0 + (x)) -#define GPIO_ALT_FN 0 -#define GPIO_SIMPLE_IO 1 - -/* GPIO Mode: 0: input mode, 1: output mode */ -#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -#define GPIO_INPUT_MODE 0 -#define GPIO_OUTPUT_MODE 1 - #endif /* SUPERIO_ITE_IT8659E_H */ diff --git a/src/superio/ite/it8712f/Kconfig b/src/superio/ite/it8712f/Kconfig index 0dfa524..81b3c62 100644 --- a/src/superio/ite/it8712f/Kconfig +++ b/src/superio/ite/it8712f/Kconfig @@ -3,3 +3,11 @@ config SUPERIO_ITE_IT8712F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + +if SUPERIO_ITE_IT8712F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 5 + +endif diff --git a/src/superio/ite/it8718f/Kconfig b/src/superio/ite/it8718f/Kconfig index 65fcdab..c17bf41 100644 --- a/src/superio/ite/it8718f/Kconfig +++ b/src/superio/ite/it8718f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8718F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8718F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig index 338ed21..3625ef6 100644 --- a/src/superio/ite/it8720f/Kconfig +++ b/src/superio/ite/it8720f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8720F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8720F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index ec22a2d..8c2e676 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -3,7 +3,15 @@ config SUPERIO_ITE_IT8721F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8721F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index be16a2d..c85e94a 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8728F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + +if SUPERIO_ITE_IT8728F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 8e9af54..6d7cf39 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED select SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8772F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8772f/Makefile.mk b/src/superio/ite/it8772f/Makefile.mk index a96a862..93ea16d 100644 --- a/src/superio/ite/it8772f/Makefile.mk +++ b/src/superio/ite/it8772f/Makefile.mk @@ -1,6 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later
-bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c -romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c -smm-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c deleted file mode 100644 index efbb035..0000000 --- a/src/superio/ite/it8772f/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <arch/io.h> -#include <device/pnp_def.h> -#include <device/pnp_ops.h> - -#include "it8772f.h" -#include "../common/ite.h" - -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ - -/* NOTICE: This file is deprecated, use ite/common instead */ - -static void it8772f_enter_conf(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8772f_exit_conf(pnp_devfn_t dev) -{ - pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); -} - -/* Configure a set of GPIOs */ -void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, - u8 pullup, u8 output, u8 enable) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(dev); - pnp_set_logical_device(dev); - if (set < 5) { - pnp_write_config(dev, GPIO_REG_SELECT(set), select); - pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); - pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); - } - pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); - pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(dev); -} - -/* Configure LED GPIOs */ -void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable, u8 led_pin_map, u8 led_freq) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(dev); - pnp_set_logical_device(dev); - if (set < 5) { - pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); - pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); - pnp_write_config(dev, GPIO_REG_SELECT(set), select); - pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); - pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); - } - pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); - pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(dev); -} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 4df21c5..a277dcd 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -11,42 +11,19 @@ #define IT8772F_GPIO 0x07 /* GPIO */ #define IT8772F_IR 0x0a /* Consumer IR */
- /* GPIO interface */ -#define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 - -#define SIO_GPIO_BLINK_GPIO10 0x08 -#define SIO_GPIO_BLINK_GPIO22 0x12 -#define SIO_GPIO_BLINK_GPIO45 0x25 - -#define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9 - -#define IT8772F_GPIO_BLINK_FREQUENCY_4_HZ (0<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_HZ (1<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_4_HZ (2<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_8_HZ (3<<1) - -#define GPIO_REG_SELECT(x) (0x25 + (x)) +#define IT8772F_GPIO_REG_SELECT(x) (0x25 + (x))
/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ -#define GPIO_REG_POLARITY(x) (0xb0 + (x)) +#define IT8772F_GPIO_REG_POLARITY(x) (0xb0 + (x))
/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ -#define GPIO_REG_PULLUP(x) (0xb8 + (x)) +#define IT8772F_GPIO_REG_PULLUP(x) (0xb8 + (x))
/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ -#define GPIO_REG_ENABLE(x) (0xc0 + (x)) +#define IT8772F_GPIO_REG_ENABLE(x) (0xc0 + (x))
/* GPIO Mode: 0: input mode, 1: output mode */ -#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) - -#include <device/pnp_type.h> -#include <stdint.h> - -void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, - u8 pullup, u8 output, u8 enable); - -void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable, u8 led_pin_map, u8 led_freq); +#define IT8772F_GPIO_REG_OUTPUT(x) (0xc8 + (x))
#endif /* SUPERIO_ITE_IT8772F_H */ diff --git a/src/superio/ite/it8783ef/Kconfig b/src/superio/ite/it8783ef/Kconfig index e1d993f..da47e45 100644 --- a/src/superio/ite/it8783ef/Kconfig +++ b/src/superio/ite/it8783ef/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8783EF bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8783EF + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8784e/Kconfig b/src/superio/ite/it8784e/Kconfig index 66dd6c9..ba19459 100644 --- a/src/superio/ite/it8784e/Kconfig +++ b/src/superio/ite/it8784e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8784E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8784E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 216d6f5..ab4a92f 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8786E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8786E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif
-
Michał Żygowski (Code Review)