Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.
Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81938?usp=email )
Change subject: soc/intel/alderlake: Enable Early CrashLog support ......................................................................
soc/intel/alderlake: Enable Early CrashLog support
Perform the SoC-specific part of preparing CrashLog, by temporarily provisioning MMIO space for the CrashLog device, and calling into the early CrashLog feature.
Change-Id: I1ce47531a74486bc5c996f7793af7087bc30d1f7 Signed-off-by: Benjamin Doron benjamin.doron@9elements.com --- M src/soc/intel/alderlake/bootblock/bootblock.c M src/soc/intel/alderlake/crashlog.c M src/soc/intel/alderlake/include/soc/iomap.h 3 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81938/1
diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a4..81de269 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> +#include <intelblocks/crashlog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -26,6 +27,10 @@ void bootblock_soc_init(void) { report_platform_info(); + + if (CONFIG(SOC_INTEL_CRASHLOG)) + early_dump_pmc_and_cpu_crashlog_from_srams(); + bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index ab2823b..8f5fbcb 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -23,6 +23,26 @@ static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
+void early_cl_enable_bars(void) +{ + /* Set CrashLog BARs (FIXME: Is there a second BAR here? Documentation doesn't say so) */ + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, (uint32_t)PCH_TEMPORARY_ADDRESS); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, 0); + + /* Enable CrashLog memory-access */ + pci_write_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY); +} + +void early_cl_disable_bars(void) +{ + /* Clear CrashLog BARs */ + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, 0); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, 0); + + /* Disable CrashLog memory-access */ + pci_write_config16(SA_DEV_TMT, PCI_COMMAND, 0); +} + u32 __weak cl_get_cpu_mb_int_addr(void) { return CRASHLOG_MAILBOX_INTF_ADDRESS; diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index b451a72..49d6665 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -100,6 +100,10 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+/* May be used for any purpose, but known to be used by the FSP. */ +#define PCH_TEMPORARY_ADDRESS 0xfe600000 +#define PCH_TEMPORARY_SIZE 0x200000 + #define IOM_BASE_ADDRESS 0xfbc10000 #define IOM_BASE_SIZE 0x1600