Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s - coreboot-gerrit

21 Mar 2022


      Attention is currently required from: Peichao Wang, Kane Chen, Tim Wawrzynczak.
Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 )
Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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Patch Set 9:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62919/comment/a7ead463_d3ef6950 
PS7, Line 643: 	s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->PcieRpAspm);
...
ok. understood.
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Gerrit-Change-Number: 62919
Gerrit-PatchSet: 9
Gerrit-Owner: Kevin Chang kevin.chang@lcfc.corp-partner.google.com
Gerrit-Reviewer: Peichao Wang pwang12@lenovo.corp-partner.google.com
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