Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61690 )
Change subject: soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock ......................................................................
soc/amd/cezanne: Add ability to dump Smart Trace Buffer in bootblock
This will make it easier to inspect the smart trace buffer. This buffer contains POST codes and other debug data that can be useful to understand what the system is doing.
This functionality was ported over from the linux amd-pmc driver.
BUG=b:217960752 TEST=Boot guybrush and verify STB is dumped
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ied3010ba0fc1d7327fe07df562f0483099d6b165 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/bootblock.c 3 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/61690/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 620c650..8518588 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -298,6 +298,11 @@ cores to transition between p-states independently. A vendor may choose to generate _PSD object to allow cores to transition together.
+config DUMP_SMART_TRACE_BUFFER + bool + help + Dumps the Smart Trace Buffer when entering bootblock. + menu "PSP Configuration Options"
config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5708baa0..177ba31 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -14,6 +14,7 @@ bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c +bootblock-y += stb.c bootblock-y += uart.c
verstage-y += i2c.c diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index c42ac0a..24c0b7e 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <cpu/x86/tsc.h> #include <soc/southbridge.h> +#include <soc/stb.h> #include <soc/psp_transfer.h> #include <stdint.h>
@@ -41,6 +42,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+ if (CONFIG(DUMP_SMART_TRACE_BUFFER)) + dump_stb(); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { verify_psp_transfer_buf(); show_psp_transfer_info();