Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58281 )
Change subject: sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 ......................................................................
sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1
Enable PCIe Clock power management and ASPM L1 substate by default. This matches what Broadwell does.
Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/lynxpoint/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 03b3e9a..25ed6ef 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -68,6 +68,12 @@ bool default y
+config PCIEXP_CLK_PM + default y + +config PCIEXP_L1_SUB_STATE + default y + config SERIALIO_UART_CONSOLE bool "Use SerialIO UART for console" depends on INTEL_LYNXPOINT_LP