[S] Change in coreboot[main]: soc/intel/xeon_sp: Make use of PCI driver for xHCI

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85808?usp=email )

Change subject: soc/intel/xeon_sp: Make use of PCI driver for xHCI
......................................................................

soc/intel/xeon_sp: Make use of PCI driver for xHCI

Instead of misusing the chip final handler move the EGB specific
code into the ebg folder and make use of the existing PCI driver
for xHCI by adding the correct PCI ID.

This allows to decouple the 10nm Xeon-SP from EBG and use the
northbridge code with a LBG PCH.

Currently no mainboard uses the code, but it should be used as
FSP always applies the default USB configuration for ArcherCity.

Change-Id: Ie3968da4c95febbb270e1dbbea8b8b1b8fc1e96d
Signed-off-by: Patrick Rudolph 
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
M src/soc/intel/xeon_sp/ebg/soc_xhci.c
M src/soc/intel/xeon_sp/include/soc/ramstage.h
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/ramstage.c
7 files changed, 17 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/85808/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 60ed807..a7a31b2d 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4538,6 +4538,7 @@
 #define PCI_DID_INTEL_PTL_U_H_XHCI		0xe37d
 #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI		0xe331
 #define PCI_DID_INTEL_SNR_XHCI			0x18d0
+#define PCI_DID_INTEL_EBG_XHCI			0x1bcd

/* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 6d35f39..da6396c 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -153,6 +153,7 @@
    PCI_DID_INTEL_ADP_M_XHCI,
    PCI_DID_INTEL_RPP_S_XHCI,
    PCI_DID_INTEL_SNR_XHCI,
+	PCI_DID_INTEL_EBG_XHCI,
    0
 };

diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
index 005a8e1..c6e9116 100644
--- a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
+++ b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
@@ -47,7 +47,7 @@
    uint32_t port;
 };

+void mainboard_override_usb_oc(void);
 void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins);
-void lock_oc_cfg(bool lock);

#endif /* _XHCI_H_ */
diff --git a/src/soc/intel/xeon_sp/ebg/soc_xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
index f8aa37b..2d3d09c 100644
--- a/src/soc/intel/xeon_sp/ebg/soc_xhci.c
+++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
@@ -2,6 +2,7 @@

#include <console/console.h>
 #include <device/pci.h>
+#include <intelblocks/xhci.h>
 #include <soc/pch_pci_devs.h>
 #include <soc/xhci.h>
 #include <types.h>
@@ -33,7 +34,7 @@
    	write32(mbar + config[i].pin, config[i].port);
 }

-void lock_oc_cfg(bool lock)
+static void lock_oc_cfg(bool lock)
 {
    uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2);

@@ -43,3 +44,15 @@
    	cfg &= ~(OCCFGDONE);
    pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg);
 }
+
+__weak void mainboard_override_usb_oc(void)
+{
+	/* Default weak implementation */
+}
+
+void soc_xhci_init(struct device *dev)
+{
+	lock_oc_cfg(false);
+	mainboard_override_usb_oc();
+	lock_oc_cfg(true);
+}
diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h
index 91dd114..9cc4ac2 100644
--- a/src/soc/intel/xeon_sp/include/soc/ramstage.h
+++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h
@@ -13,7 +13,6 @@
 void mainboard_override_fsp_gpio(void);
 /* lock or unlock community B and D pads after FSP-S */
 void lock_gpio(bool lock);
-void mainboard_override_usb_oc(void);

extern struct pci_operations soc_pci_ops;

diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index 9fd747d..f1e9de2 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -71,10 +71,6 @@

p2sb_hide();

-	/* Accessing xHCI CSR needs to be done after PCI enumeration. */
-	lock_oc_cfg(false);
-	mainboard_override_usb_oc();
-	lock_oc_cfg(true);
    /* Disable CPU Crashlog to avoid conflict between CPU Crashlog and BMC ACD. */
    disable_cpu_crashlog();
 }
diff --git a/src/soc/intel/xeon_sp/spr/ramstage.c b/src/soc/intel/xeon_sp/spr/ramstage.c
index 6ac3efe..e1ede29 100644
--- a/src/soc/intel/xeon_sp/spr/ramstage.c
+++ b/src/soc/intel/xeon_sp/spr/ramstage.c
@@ -23,8 +23,3 @@
 {
    /* Default weak implementation */
 }
-
-__weak void mainboard_override_usb_oc(void)
-{
-	/* Default weak implementation */
-}