Attention is currently required from: Felix Singer, Nico Huber, Subrata Banik, Michael Niewöhner, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60946 )
Change subject: soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
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Patch Set 1:
(1 comment)
Patchset:
PS1:
Actually, I just remembered we rely on the FSP UPD defaults, right? still in […]
also looks like the FSP has an assert (debug mode only ?) if a port with hotplug support does *not* have slotImplemented set to 1 for that port, so that needs to be coordinated probably in fsp_params.c
Also I agree with you w/r/t UPD defaults.... I should add a TODO for myself to make sure we are programming all of the visible UPDs.
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