Patch set updated for coreboot: ce986db haswell: use asmlinkage for assembly-called funcs

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3203

-gerrit

commit ce986db233197f24f23be4c6310a1f088b74c7d1
Author: Aaron Durbin 
Date:   Thu May 2 09:42:13 2013 -0500

haswell: use asmlinkage for assembly-called funcs

When the haswell MP/SMM code was developed it was using a coreboot
    repository that did not contain the asmlinkage macro. Now that the
    asmlinkage macro exists use it.

BUG=None
    BRANCH=None
    TEST=Built and booted.

Change-Id: I662f1b16d1777263b96a427334fff8f98a407755
    Signed-off-by: Aaron Durbin 
---
 src/cpu/intel/haswell/haswell.h     | 4 +++-
 src/cpu/intel/haswell/mp_init.c     | 3 +--
 src/cpu/intel/haswell/romstage.c    | 2 +-
 src/cpu/intel/haswell/smmrelocate.c | 2 +-
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index a1c6f39..8f4368f 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -22,6 +22,8 @@
 #ifndef _CPU_INTEL_HASWELL_H
 #define _CPU_INTEL_HASWELL_H

+#include <arch/cpu.h>
+
 /* Haswell bus clock is fixed at 100MHz */
 #define HASWELL_BCLK		100

@@ -148,7 +150,7 @@ void romstage_common(const struct romstage_params *params);
  *  +32: MTTR mask 1 63:32
  *  ...
  */
-void * __attribute__((regparm(0))) romstage_main(unsigned long bist);
+void * asmlinkage romstage_main(unsigned long bist);
 /* romstage_after_car() is the C function called after cache-as-ram has
  * been torn down. It is responsible for loading the ramstage. */
 void romstage_after_car(void);
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index ddcff6c..deba629 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -150,8 +150,7 @@ static void cleanup_rom_caching(void)

/* By the time APs call ap_init() caching has been setup, and microcode has
  * been loaded. */
-static void __attribute__((cdecl))
-ap_init(unsigned int cpu, void *microcode_ptr)
+static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr)
 {
    struct cpu_info *info;

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ff57584..077e409 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -162,7 +162,7 @@ static void *setup_romstage_stack_after_car(void)
    return slot;
 }

-void * __attribute__((regparm(0))) romstage_main(unsigned long bist)
+void * asmlinkage romstage_main(unsigned long bist)
 {
    int i;
    void *romstage_stack_after_car;
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index a8ab841..6caeafa 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -164,7 +164,7 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
 /* The relocation work is actually performed in SMM context, but the code
  * resides in the ramstage module. This occurs by trampolining from the default
  * SMRAM entry point to here. */
-static void __attribute__((cdecl))
+static void asmlinkage
 cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime)
 {
    msr_t mtrr_cap;