New patch to review for coreboot: mainboard/ibase: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16909
-gerrit
commit 1352379d69123cd1fa99d5937bf1d20df4e88624 Author: Elyes HAOUAS ehaouas@noos.fr Date: Thu Oct 6 19:52:38 2016 +0200
mainboard/ibase: Use C89 comments style & remove commented code
Change-Id: I3e51b75bd63605d832f337c4d8797b2b3c965394 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/ibase/mb899/irq_tables.c | 20 ++++++------- src/mainboard/ibase/mb899/mainboard.c | 4 +-- src/mainboard/ibase/mb899/mptable.c | 10 +++---- src/mainboard/ibase/mb899/romstage.c | 48 ++++++++++++++----------------- src/mainboard/ibase/mb899/superio_hwm.c | 51 ++++++++++++++------------------- 5 files changed, 61 insertions(+), 72 deletions(-)
diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index 9c8a5cc..aaa6677 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet Marvell 88E8053 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 376e08a..24f807b 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -24,8 +24,8 @@
-// mainboard_enable is executed as first thing after -// enumerate_buses(). +/* mainboard_enable is executed as first thing after */ +/* enumerate_buses(). */
static void mainboard_enable(device_t dev) { diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 89fba6b..440929d 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v) firewire_bus); }
- // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the - // highest bus number on the pci bus. + /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */ + /* highest bus number on the pci bus. */ riser = dev_find_device(0x3388, 0x0021, 0); if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); @@ -94,11 +94,11 @@ static void *smp_write_config_table(void *v)
if (riser) { /* Old riser card */ - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
/* New Riser Card */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 3fa339f..13b68c0 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */
-// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
#include <stdint.h> #include <string.h> @@ -56,15 +56,15 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void) { - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range + /* Set COM1/COM2 decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 + /* Enable COM1/COM2/KBD/SuperIO1+2 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0x290 + /* Enable HWM at 0x290 */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); - // io 0x300 decode + /* io 0x300 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); }
@@ -79,13 +79,13 @@ static void early_superio_config_w83627ehg(void) dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev);
- pnp_write_config(dev, 0x24, 0xc4); // PNPCSV + pnp_write_config(dev, 0x24, 0xc4); /* PNPCSV */
- pnp_write_config(dev, 0x29, 0x01); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 - pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? - pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? - pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? + pnp_write_config(dev, 0x29, 0x01); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings should be fc but gets set to 02 */ + pnp_write_config(dev, 0x2b, 0xc0); /* GPIO settings? */ + pnp_write_config(dev, 0x2c, 0x03); /* GPIO settings? */ + pnp_write_config(dev, 0x2d, 0x20); /* GPIO settings? */
dev = PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); @@ -99,27 +99,25 @@ static void early_superio_config_w83627ehg(void) pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1);
- dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + dev = PNP_DEV(0x4e, W83627EHG_KBC); /* Keyboard */ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1);
dev = PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it + pnp_set_enable(dev, 1); /* Just enable it */
dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */
dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); @@ -142,8 +140,6 @@ static void early_superio_config_w83627ehg(void) static void rcba_config(void) { /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; @@ -161,7 +157,7 @@ static void rcba_config(void) RCBA8(0x31ff) = 0x03;
/* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + }
static void early_ich7_init(void) @@ -169,15 +165,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32;
- // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
- // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
- // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -211,7 +207,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7);
- // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7fb45f9..b1dd21e 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -29,7 +29,6 @@ #define FAN_CRUISE_CONTROL_THERMAL 2
#define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0
#define HWM_BASE 0x290
@@ -49,8 +48,8 @@ struct fan_speed { u16 fan_speed; };
-// FANIN Target Speed Register -// FANIN = 337500 / RPM +/* FANIN Target Speed Register */ +/* FANIN = 337500 / RPM */ struct fan_speed fan_speeds[] = { { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, @@ -80,34 +79,28 @@ void hwm_setup(void) get_option(&cpufan_control, "cpufan_cruise_control"); cpufan_speed = FAN_SPEED_5625; get_option(&cpufan_speed, "cpufan_speed"); - //cpufan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&cpufan_temperature, "cpufan_temperature"); +
sysfan_control = FAN_CRUISE_CONTROL_DISABLED; get_option(&sysfan_control, "sysfan_cruise_control"); sysfan_speed = FAN_SPEED_5625; get_option(&sysfan_speed, "sysfan_speed"); - //sysfan_temperature = FAN_TEMPERATURE_30DEGC; - //get_option(&sysfan_temperature, "sysfan_temperature"); - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit
hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + hwm_write(0x59, 0x20); /* Diode Selection */ + hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */
hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset + hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */ + hwm_write(0x55, 0x19); /* CPUTIN temperature offset */ + hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */
- hwm_bank(0x80); // Default + hwm_bank(0x80); /* Default */
u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode + /* 00 FANOUT is Manual Mode */ + /* 01 FANOUT is Thermal Cruise Mode */ + /* 10 FANOUT is Fan Speed Cruise Mode */ switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; @@ -116,20 +109,20 @@ void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; } - // This register must be written first + /* This register must be written first */ hwm_write(0x04, fan_config);
switch (cpufan_control) { case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); /* CPUFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", temperatures[cpufan_temperature].deg_celsius, temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); /* CPUFANIN target temperature */ break; }
@@ -137,21 +130,21 @@ void hwm_setup(void) case FAN_CRUISE_CONTROL_SPEED: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); /* SYSFANIN target speed */ break; case FAN_CRUISE_CONTROL_THERMAL: printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", temperatures[sysfan_temperature].deg_celsius, temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */ break; }
- hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time + hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */ + hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */
- hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + hwm_write(0x47, 0xaf); /* FAN divisor register */ + hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */
- hwm_write(0x40, 0x01); // Init, but no SMI# + hwm_write(0x40, 0x01); /* Init, but no SMI# */ }
-
HAOUAS Elyes