Patch set updated for coreboot: caefe20 haswell: enable cache-as-ram migration

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3236

-gerrit

commit caefe206ae31bc3301ba60805cc792024214dbc0
Author: Aaron Durbin 
Date:   Fri May 10 00:51:43 2013 -0500

haswell: enable cache-as-ram migration

The haswell code allows for vboot ramstage verification.
    However, that code path relies on accessing global cache-as-ram
    variables after cache-as-ram is torn down. In order to avoid
    that situation enable cache-as-ram migration.

cbmemc_reinit() no longer needs to be called from romstage
    because it is invoked automatically by the cache-as-ram
    migration infrastructure.

Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
    Signed-off-by: Aaron Durbin 
---
 src/cpu/intel/haswell/Kconfig    | 1 +
 src/cpu/intel/haswell/romstage.c | 5 -----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 152059f..4c61b2d 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
    #select AP_IN_SIPI_WAIT
    select TSC_SYNC_MFENCE
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select CAR_MIGRATION

config BOOTBLOCK_CPU_INIT
    string
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 1093e6b..8196273 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -188,11 +188,6 @@ void * asmlinkage romstage_main(unsigned long bist)
    /* Get the stack to use after cache-as-ram is torn down. */
    romstage_stack_after_car = setup_romstage_stack_after_car();

-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
-
    return romstage_stack_after_car;
 }