[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 88:

(3 comments)

Patchset:

PS81:
> > @mishra.saurabh@intel. […]

Sure, updated to align with `CB:84217` and `CB:84220`.
However, PTL is aligned with `CB:84183`

But, this `CB:84182`, PTL do not use include/soc/itss.h, it is already using `src/soc/intel/common/block/include/intelblocks/itss.h`

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83798/comment/76667a39_be8d9c8c?usp... :
PS75, Line 381: config DROP_CPU_FEATURE_PROGRAM_IN_FSP
> keep this by making `default n`

Sure, done.

File src/soc/intel/pantherlake/retimer.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/53a87579_a0b2562c?usp... :
PS71, Line 19: 
             : 	for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
> > Hi, declaring variables of the same type together in for loop is accepted in c. […]

Done