Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56681 )
Change subject: mb/google/brya: Update descriptor region for board ID 2 ......................................................................
mb/google/brya: Update descriptor region for board ID 2
brya0 boards with board ID 2 can support a 50MHz SPI flash speed, therefore modify the descriptor on the first boot to change the fast read, write, erase, and status read speeds to 50 MHz.
BUG=b:188577893
Change-Id: Ibc4cca72f72eceededf2790f28124e46a02d12dc Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/brya0/Makefile.inc A src/mainboard/google/brya/variants/brya0/bootblock.c 2 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56681/1
diff --git a/src/mainboard/google/brya/variants/brya0/Makefile.inc b/src/mainboard/google/brya/variants/brya0/Makefile.inc index cd8eb69..319ad98 100644 --- a/src/mainboard/google/brya/variants/brya0/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += gpio.c +bootblock-y += bootblock.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/brya0/bootblock.c b/src/mainboard/google/brya/variants/brya0/bootblock.c new file mode 100644 index 0000000..6a7228e --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/bootblock.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <types.h> + +static bool update_spi_freq(uint8_t *buf) +{ + struct flcomp { + uint32_t dontcare0 : 20; + uint32_t fast_read : 1; + uint32_t fast_read_freq : 3; + uint32_t write_erase_freq : 3; + uint32_t read_status_freq : 3; + uint32_t dontcare1 : 2; + } *flcomp = (struct flcomp *)(buf + 0x30); + enum { + FREQ_100MHZ = 0x00, + FREQ_50MHZ = 0x01, + FREQ_33MHZ = 0x03, + FREQ_25MHZ = 0x04, + FREQ_14MHZ = 0x06, + }; + + /* Only applicable to board ID 2 */ + if (board_id() != 2) + return false; + + if (flcomp->fast_read_freq == FREQ_50MHZ && + flcomp->write_erase_freq == FREQ_50MHZ && + flcomp->read_status_freq == FREQ_50MHZ && + flcomp->fast_read == 0x01) + return false; + + flcomp->fast_read_freq = FREQ_50MHZ; + flcomp->write_erase_freq = FREQ_50MHZ; + flcomp->read_status_freq = FREQ_50MHZ; + flcomp->fast_read = 0x01; + return true; +} + +bool variant_update_descriptor(uint8_t *desc) +{ + return update_spi_freq(desc); +}