Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 38:
(4 comments)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/4225cd5a_5d6575d8?usp... :
PS17, Line 38: GPP_ASPIO
I have changed GPP_ASPI0 to GPP_A in other places.
Done
https://review.coreboot.org/c/coreboot/+/83789/comment/bb55eedd_ecd18472?usp... :
PS17, Line 73: .num_groups = ARRAY_SIZE(ptl_community0_groups),
in progress. Some further check needed. […]
Subrata, Same as cpu_port. I'd like to know your opinion on this due to the 16-bit port id changes needed for this.
https://review.coreboot.org/c/coreboot/+/83789/comment/a7c677d5_edd2bef0?usp... :
PS17, Line 177: { PMC_GPP_E, GPP_E },
sure. will make the changes.
Done
File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/83789/comment/5a29f525_9976d35e?usp... :
PS17, Line 544: #define GPP_VGPIO0 246
in progress.
The response is that these are for internal only and there is no plan to provide VGPIO info in EDS.
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