Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit ee3e1eda36b76c53a8789e04383910570abeb174 Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Jan 31 19:38:11 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside
Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ENABLE_DEBUG_LED_FINDFSP" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing.
TEST=Build and run on Galileo Gen2
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/Kconfig | 93 +++++++++++- src/soc/intel/quark/Makefile.inc | 8 + src/soc/intel/quark/memmap.c | 7 + src/soc/intel/quark/romstage/Makefile.inc | 9 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 205 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/esram_init.inc | 24 ++- 6 files changed, 344 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2509e06..6bbb45e 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -38,6 +38,97 @@ config CBFS_SIZE This option specifies the maximum size of the CBFS portion in the firmware image.
+config ENABLE_DEBUG_LED + bool + default n + help + Enable the use of the SD LED for early debugging before serial output + is available. Setting this LED indicates that control has reached the + desired check point. + +config ENABLE_DEBUG_LED_ESRAM + bool "SD LED indicates ESRAM initialized" + default n + select ENABLE_DEBUG_LED + help + Indicate that ESRAM has been successfully initialized. + +config ENABLE_DEBUG_LED_FINDFSP + bool "SD LED indicates fsp.bin file was found" + default n + select ENABLE_DEBUG_LED + help + Indicate that fsp.bin was found. + +config ENABLE_DEBUG_LED_TEMPRAMINIT + bool "SD LED indicates TempRamInit was successful" + default n + select ENABLE_DEBUG_LED + help + Indicate that TempRamInit was successful. + +if PLATFORM_USES_FSP1_1 + +config FSP_FILE + string "Intel FSP binary path and filename" + default "3rdparty/blobs/soc/intel/quark/fsp.bin" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_IMAGE_ID_STRING + string "8 byte platform string identifying the FSP platform" + default "QUK-FSP0" + help + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. + +config FSP_LOC + hex + default 0xfff80000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + +config FSP_PDAT_FILE + string + default "3rdparty/blobs/soc/intel/quark/pdat.bin" + help + The path and filename of the Intel Galileo platform-data-patch (PDAT) + binary. This binary file is generated by the platform-data-patch.py + script released with the Quark BSP. + +config FSP_PDAT_LOC + hex + default 0xfff10000 + help + The location in CBFS that the PDAT is located. It must match the + PCD PcdPlatformDataBaseAddress of Quark SoC FSP. + +config FSP_SRAM_LOC + hex + default 0x80000000 + help + The location in SRAM where a copy of the FSP binary is placed. + +config HAVE_FSP_PDAT_FILE + bool + default n + help + The PDAT file is required for the FSP 1.1 binary + +config HAVE_FSP_RAW_BIN + bool "Add the Intel FSP binary to the flash image without relocation" + default n + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + +endif # PLATFORM_USES_FSP1_1 + config HAVE_RMU_FILE bool default n @@ -46,7 +137,7 @@ config HAVE_RMU_FILE
config RMU_FILE string - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" + default "3rdparty/blobs/soc/intel/quark/rmu.bin" depends on HAVE_RMU_FILE help The path and filename of the Intel Quark RMU binary. diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index c8295cb..f7a629e 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -29,6 +29,14 @@ CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+# Add the platform data file to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_PDAT_FILE),y) +cbfs-files-y += pdat.bin +pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) +pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) +pdat.bin-type := raw +endif # CONFIG_HAVE_FSP_PDAT_FILE + ifeq ($(CONFIG_HAVE_RMU_FILE),y) cbfs-files-y += rmu.bin rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 2edfdc4..71e4784 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,6 +14,13 @@ */
#include <cbmem.h> +#include <fsp/memmap.h> + +size_t mmap_region_granularity(void) +{ + /* Align to 8 MiB by default */ + return 8 << 20; +}
void *cbmem_top(void) { diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index a0be5d5..6412825 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -14,3 +14,12 @@ #
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc +cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +# Add the FSP binary to the CBFS image +ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) +cbfs-files-y += fsp.bin +fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) +fsp.bin-position := $(CONFIG_FSP_LOC) +fsp.bin-type := raw +endif # CONFIG_HAVE_FSP_RAW_BIN diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc new file mode 100644 index 0000000..e589ada --- /dev/null +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Replacement for cache_as_ram.inc when using the FSP binary. This code + * locates the FSP binary, initializes the cache as RAM and performs the + * first stage of initialization. Next this code switches the stack from + * the cache to RAM and then disables the cache as RAM. Finally this code + * performs the final stage of initialization. + */ + +#include <rules.h> + + /* + * eax: BIST value + */ + + movl %eax, %edi + +cache_as_ram: + post_code(0x20) + + /* + * edi: BIST value + */ + + /* + * Find the FSP binary in cbfs. + * Make a fake stack that has the return value back to this code. + */ + lea fake_fsp_stack, %esp + jmp find_fsp + +find_fsp_ret: + /* Save the FSP location */ + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_SRAM_LOC, %eax + jbe halt1 + + post_code(POST_FSP_TEMP_RAM_INIT) + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + + /* Calculate entry into FSP */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + */ + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + */ + + cmp $0, %eax + jne halt2 + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT) + movl %edx, %esi + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + movl %esi, %edx + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ + + clrl %eax + jmp .Lhlt + +halt1: + /* + * Failures for postcode 0xBA - failed in fsp_fih_early_find() + * + * Values are: + * 0x01 - FV signature, "_FVH" not present + * 0x02 - FFS GUID not present + * 0x03 - FSP INFO Header not found + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to + * a different location, or does it need to be? + * 0x05 - FSP INFO Header signature "FSPH" not found + * 0x06 - FSP Image ID is not the expected ID. + */ + movb $0xBA, %ah + jmp .Lhlt + +halt2: + /* + * Failures for postcode 0xBB - failed in the FSP: + * + * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked + */ + movb $0xBB, %ah + jmp .Lhlt + +#---------------------------------------------------------------------------- +# +# Procedure: .Lhlt +# +# Input: ah - Upper 8-bits of POST code +# al - Lower 8-bits of POST code +# +# Description: +# Infinite loop displaying alternating POST code values +# +#---------------------------------------------------------------------------- + +#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ +#define POST_DELAY 0x50 + +.Lhlt: + xchg %al, %ah + mov $POST_DELAY, %dh +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif +.flash_setup: + movl $FLASH_DELAY, %ecx +.flash_delay: + outb %al, $0xED + loop .flash_delay +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %dl + xorb $1, %dl + movb %dl, 0(%ebx) +#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ + decb %dh + jnz .flash_setup + jmp .Lhlt + +/* + * esp is set to this location so that the call into and return from the FSP + * in find_fsp will work. + */ + .align 4 +fake_fsp_stack: + .long find_fsp_ret + .long CONFIG_FSP_SRAM_LOC /* FSP base address */ + +CAR_init_params: + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc index ed695b3..9414f90 100644 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -526,6 +526,24 @@ stackless_PCIConfig_Read:
esram_init_done:
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + + # + # Copy FSP image to SRAM and call it. + # + #TODO - FSP location/size could be got in a routine. + cld + movl $(0x00040000), %ecx # 256K DWORDs = 64K + shrl $2, %ecx + movl $CONFIG_FSP_LOC, %esi # The source address. + movl $CONFIG_FSP_SRAM_LOC, %edi # FSP destination in ESRAM + rep movsl +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +sd_led: + movl %eax, %ecx + .equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller .equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space .equ SD_CFG_CMD, (SD_CFG_BASE+0x04) # Command register in PCI config space @@ -566,9 +584,13 @@ L43: jmp stackless_PCIConfig_Read
L44: +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) movl $SD_HOST_CTRL, %ebx movb 0(%ebx), %al orb $1, %al movb %al, 0(%ebx) - jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ + + movl %ecx, %eax +#endif /* CONFIG_ENABLE_DEBUG_LED */
-
Leroy P Leahy