Change in coreboot[master]: soc/amd/picasso: Add UPDs for support edp power sequence adjust

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to review the following change.

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 2e6f8d4..8921d4e 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -244,6 +244,17 @@
    	uint8_t   boostadj;
    	uint16_t  margin_deemph;
    } edp_tuningset;
+
+	/* edp panel power sequence control*/
+	uint8_t edp_pwr_adjust_enable;
+	uint8_t pwron_digon_to_De;
+	uint8_t pwron_de_to_varybl;
+	uint8_t pwrdown_varybloff_to_de;
+	uint8_t pwrdown_de_to_digoff;
+	uint8_t pwroff_delay;
+	uint8_t pwron_varybl_to_blon;
+	uint8_t pwrdown_bloff_to_varybloff;
+	uint8_t min_allowed_bl_level;
 };

#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 86b3eba..3a1a579 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -155,6 +155,17 @@
    	scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
    	scfg->BoostAdj = cfg->edp_tuningset.boostadj;
    }
+	if (cfg->edp_pwr_adjust_enable) {
+		scfg->pwron_digon_to_De = cfg->pwron_digon_to_De;
+		scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl;
+		scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de;
+		scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff;
+		scfg->pwroff_delay = cfg-> pwroff_delay;
+		scfg->pwron_varybl_to_blon =	cfg-> pwron_varybl_to_blon;
+		scfg->pwrdown_bloff_to_varybloff = cfg-> pwrdown_bloff_to_varybloff;
+		scfg->min_allowed_bl_level = cfg-> min_allowed_bl_level;
+	}
+
 }

void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/48864/1/src/soc/amd/picasso/fsp_par... 
File src/soc/amd/picasso/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/48864/1/src/soc/amd/picasso/fsp_par... 
PS1, Line 163: 		scfg->pwroff_delay = cfg-> pwroff_delay;
spaces prohibited around that '->' (ctx:VxW)

https://review.coreboot.org/c/coreboot/+/48864/1/src/soc/amd/picasso/fsp_par... 
PS1, Line 164: 		scfg->pwron_varybl_to_blon =	cfg-> pwron_varybl_to_blon;
spaces prohibited around that '->' (ctx:VxW)

https://review.coreboot.org/c/coreboot/+/48864/1/src/soc/amd/picasso/fsp_par... 
PS1, Line 165: 		scfg->pwrdown_bloff_to_varybloff = cfg-> pwrdown_bloff_to_varybloff;
spaces prohibited around that '->' (ctx:VxW)

https://review.coreboot.org/c/coreboot/+/48864/1/src/soc/amd/picasso/fsp_par... 
PS1, Line 166: 		scfg->min_allowed_bl_level = cfg-> min_allowed_bl_level;
spaces prohibited around that '->' (ctx:VxW)

[chris wang (Code Review)]

Hello Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/2

[chris wang (Code Review)]

Attention is currently required from: chris wang.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#4).

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/4

[Nikolai Vyssotski (Code Review)]

Attention is currently required from: chris wang.
Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

Patch Set 6:

(3 comments)

Patchset:

PS6: 
It seems the commit name is a bit misleading and being reused from the previous commit in the patch train. Maybe something along the lines of initializing the eDP UPDs?

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/f911913f_9dcc7c4b 
PS6, Line 251: 	uint8_t edp_pwr_adjust_enable;
It is maybe worth mentioning here that all the values below are in units of 4ms as you have in commit message.

https://review.coreboot.org/c/coreboot/+/48864/comment/2291c2b9_2e9f2a49 
PS6, Line 252: pwron_digon_to_De
Odd variable name. Perhaps pwron_digon_to_de

[chris wang (Code Review)]

Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#9).

Change subject: soc/amd/picasso: Add UPDs for support edp power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/9

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: chris wang.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#10).

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/10

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Nikolai Vyssotski.
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 10:

(2 comments)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/06667c06_513a8706 
PS6, Line 251: 	uint8_t edp_pwr_adjust_enable;
> It is maybe worth mentioning here that all the values below are in units of 4ms as you have in commi […]

Done

https://review.coreboot.org/c/coreboot/+/48864/comment/fe9d2147_6e1c625c 
PS6, Line 252: pwron_digon_to_De
> Odd variable name. […]

Done

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Nikolai Vyssotski.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Chris Wang, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#11).

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP power sequence adjust

Add UPDs for edp power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/11

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[EricR Lai (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, chris wang.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 13: Code-Review+1

(1 comment)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/d1d28720_e81ffc71 
PS13, Line 247: 	/* edp panel power sequence control
nits: eDP, and warp the first line. Format should be
/*
 * eDP....
 */

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski.
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Kangheui Won, Nikolai Vyssotski, Chris Wang, EricR Lai, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#14).

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP power sequence adjust

Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/14

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, EricR Lai.
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 14:

(1 comment)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/9b208870_7d30489f 
PS13, Line 247: 	/* edp panel power sequence control
> nits: eDP, and warp the first line. Format should be […]

Done

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[EricR Lai (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, chris wang.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 14: Code-Review+2

(1 comment)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/760b3284_bcb9649c 
PS14, Line 248: edp
nits: eDP ,you missed this.

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, chris wang.
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Kangheui Won, Nikolai Vyssotski, Chris Wang, EricR Lai, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48864

to look at the new patch set (#16).

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP power sequence adjust

Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48864/16

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[chris wang (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, EricR Lai.
chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 16:

(1 comment)

File src/soc/amd/picasso/chip.h:

https://review.coreboot.org/c/coreboot/+/48864/comment/d10f4d64_672ed27b 
PS14, Line 248: edp
> nits: eDP ,you missed this.

Done

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[EricR Lai (Code Review)]

Attention is currently required from: Furquan Shaikh, Kangheui Won, Nikolai Vyssotski, chris wang.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

Patch Set 16: Code-Review+2

Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP power sequence adjust

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48864 )

Change subject: soc/amd/picasso: Add UPDs for support eDP power sequence adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP power sequence adjust

Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang 
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 9498303..be30efa 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -243,6 +243,20 @@
    	uint8_t boostadj;
    	uint16_t margin_deemph;
    } edp_tuningset;
+
+	/*
+	 * eDP panel power sequence control
+	 * all pwr sequence numbers below are in uint of 4ms and "0" as default value
+	 */
+	uint8_t edp_pwr_adjust_enable;
+	uint8_t pwron_digon_to_de;
+	uint8_t pwron_de_to_varybl;
+	uint8_t pwrdown_varybloff_to_de;
+	uint8_t pwrdown_de_to_digoff;
+	uint8_t pwroff_delay;
+	uint8_t pwron_varybl_to_blon;
+	uint8_t pwrdown_bloff_to_varybloff;
+	uint8_t min_allowed_bl_level;
 };

#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 3a27a16..731a564 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -152,6 +152,17 @@
    	scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
    	scfg->BoostAdj = cfg->edp_tuningset.boostadj;
    }
+	if (cfg->edp_pwr_adjust_enable) {
+		scfg->pwron_digon_to_de = cfg->pwron_digon_to_de;
+		scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl;
+		scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de;
+		scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff;
+		scfg->pwroff_delay = cfg->pwroff_delay;
+		scfg->pwron_varybl_to_blon = cfg->pwron_varybl_to_blon;
+		scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff;
+		scfg->min_allowed_bl_level = cfg->min_allowed_bl_level;
+	}
+
 }

void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)