Change in coreboot[master]: soc/intel/common: Add support to control CSE firmware update

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62715 )

Change subject: soc/intel/common: Add support to control CSE firmware update
......................................................................

soc/intel/common: Add support to control CSE firmware update

The patch adds support to control CSE Lite firmware update dynamically.

BUG=b:153410586
TEST=Verified controlling CSE Lite firmware update dynamically on Brya

Signed-off-by: Sridhar Siricilla 
Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba
---
M src/soc/intel/common/basecode/debug/debug_feature.c
M src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
M src/soc/intel/common/block/cse/cse_lite.c
3 files changed, 29 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/62715/1

diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c
index 3f51e06..32c88d8 100644
--- a/src/soc/intel/common/basecode/debug/debug_feature.c
+++ b/src/soc/intel/common/basecode/debug/debug_feature.c
@@ -11,7 +11,8 @@
 #define PRE_MEM_FEATURE_CTRL_SZ		64

struct pre_mem_ft {
-	uint8_t reserved[64];
+	uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */
+	uint8_t reserved[63];
 };

static struct pre_mem_ft pre_mem_debug;
@@ -19,6 +20,14 @@
 _Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256,
    	"sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes");

+bool is_debug_cse_fw_update_disable(void)
+{
+	printk(BIOS_DEBUG, "rt_debug: pre_mem_debug.cse_fw_update_disable=%d\n",
+			pre_mem_debug.cse_fw_update_disable);
+
+	return pre_mem_debug.cse_fw_update_disable == 1;
+}
+
 uint8_t pre_mem_debug_init(void)
 {
    struct region_device desc_rdev;
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
index 7cd48a9..f356cbc 100644
--- a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
+++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
@@ -3,6 +3,9 @@
 #ifndef SOC_INTEL_COMMON_BASECODE_RT_DEBUG_H
 #define SOC_INTEL_COMMON_BASECODE_RT_DEBUG_H

+/* Check if CSE firmware update is enabled or not */
+bool is_debug_cse_fw_update_disable(void);
+
 /*
  * Reads OEM Section area in the Descriptor Region and
  * populates pre_mem_debug structure.
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 67dae1c..1f57571 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -9,6 +9,7 @@
 #include <security/vboot/vboot_common.h>
 #include <security/vboot/misc.h>
 #include <soc/intel/common/reset.h>
+#include <intelbasecode/debug_feature.h>
 #include <arch/cpu.h>

#define BPDT_HEADER_SZ		sizeof(struct bpdt_header)
@@ -662,6 +663,17 @@
    return true;
 }

+static bool is_cse_fw_update_enabled(void)
+{
+	if (!CONFIG(SOC_INTEL_CSE_RW_UPDATE))
+		return false;
+
+	if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
+		return !is_debug_cse_fw_update_disable();
+
+	return true;
+}
+
 static enum csme_failure_reason cse_update_rw(const struct cse_bp_info *cse_bp_info,
    	const void *cse_cbfs_rw, const size_t cse_blob_sz,
    	struct region_device *target_rdev)
@@ -1052,10 +1064,11 @@
    	cse_trigger_vboot_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR);

/*
-	 * If SOC_INTEL_CSE_RW_UPDATE is defined , then trigger CSE firmware update. The driver
-	 * triggers recovery if CSE CBFS RW metadata or CSE CBFS RW blob is not available.
+	 * cse firmware update is skipped if SOC_INTEL_CSE_RW_UPDATE is not defined and
+	 * runtime debug control flag is not enabled. The driver triggers recovery if CSE CBFS
+	 * RW metadata or CSE CBFS RW blob is not available.
     */
-	if (CONFIG(SOC_INTEL_CSE_RW_UPDATE)) {
+	if (is_cse_fw_update_enabled()) {
    	uint8_t rv;
    	rv = cse_fw_update(&cse_bp_info.bp_info);
    	if (rv)