Change in coreboot[master]: soc/intel/skylake: search for PME wake event on all root ports
Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add the ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 38 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/1
diff --git a/src/include/elog.h b/src/include/elog.h index 0574819..6dc0423 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -140,15 +140,27 @@ #define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 #define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 #define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 -#define ELOG_WAKE_SOURCE_PME_SATA 0x17 -#define ELOG_WAKE_SOURCE_PME_CSE 0x18 -#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 -#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a -#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b -#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e -#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x17 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x18 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x19 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x1a +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x1b +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x1c +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x1d +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x1e +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x22 +#define ELOG_WAKE_SOURCE_PME_SATA 0x23 +#define ELOG_WAKE_SOURCE_PME_CSE 0x24 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x25 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x26 +#define ELOG_WAKE_SOURCE_PME_XHCI 0x27 +#define ELOG_WAKE_SOURCE_PME_XDCI 0x28 +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x29 +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x2a +#define ELOG_WAKE_SOURCE_PME_WIFI 0x2b
struct elog_event_data_wake { u8 source; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..355e8ce 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -121,13 +121,14 @@ #define RP_PME_STS_BIT (1 << 16) static void pch_log_rp_wake_source(void) { - size_t i; + uint8_t i; #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else struct device *dev; #endif uint32_t val; + uint8_t maxports;
struct pme_status_info pme_status_info[] = { { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, @@ -142,9 +143,23 @@ { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, };
- for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + maxports = min(CONFIG(MAX_ROOT_PORTS), ARRAY_SIZE(pme_status_info)); + + for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev;
if (!dev)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35764
to look at the new patch set (#2).
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add the ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 38 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35764
to look at the new patch set (#3).
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add the ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 38 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/3/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/3/src/soc/intel/skylake/elog.... PS3, Line 124: uint8_t i; Why change the type?
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35764
to look at the new patch set (#4).
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add the ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 37 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/4
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/3/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/3/src/soc/intel/skylake/elog.... PS3, Line 124: uint8_t i;
Why change the type?
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 4:
*ping*
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 4:
*ping*
Please mention ELOG in the commit summary and add some ELOG expert(s) as reviewer. I don't see where the events are consumed, so it looks like you are changing an external interface.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Uploaded patch set 5: Commit message was updated.
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35764
to look at the new patch set (#5).
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 37 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... PS5, Line 159: maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); This change should also be mentioned in the commit message.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... PS5, Line 159: maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
This change should also be mentioned in the commit message.
what exactly?
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... PS5, Line 159: maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
what exactly?
"port 13-24, if they exist"
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 5: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/5/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/35764/5/src/include/elog.h@a143 PS5, Line 143: #define ELOG_WAKE_SOURCE_PME_SATA 0x17 Please don't change the numbers. These are like timestamps in that they need to be consistent once they were deployed. You'll need to append.
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Richard Spiegel, Paul Menzel, build bot (Jenkins), Daniel Kurtz, Furquan Shaikh, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35764
to look at the new patch set (#6).
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 28 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35764/6
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Uploaded patch set 6.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 6: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... File src/soc/intel/skylake/elog.c:
https://review.coreboot.org/c/coreboot/+/35764/5/src/soc/intel/skylake/elog.... PS5, Line 159: maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
"port 13-24, if they exist"
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35764 )
Change subject: soc/intel/skylake: search for PME wake event on all root ports ......................................................................
soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/include/elog.h M src/soc/intel/skylake/elog.c 2 files changed, 28 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/include/elog.h b/src/include/elog.h index 0574819..0328a86 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -149,6 +149,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b
struct elog_event_data_wake { u8 source; diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..7951394 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -121,7 +121,7 @@ #define RP_PME_STS_BIT (1 << 16) static void pch_log_rp_wake_source(void) { - size_t i; + size_t i, maxports; #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; #else @@ -142,9 +142,23 @@ { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 }, + { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 }, + { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 }, + { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 }, + { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 }, + { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 }, + { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 }, + { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 }, + { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 }, + { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 }, + { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 }, + { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 }, };
- for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + maxports = min(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info)); + + for (i = 0; i < maxports; i++) { dev = pme_status_info[i].dev;
if (!dev)
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)