[XS] Change in coreboot[main]: sb/intel/ibexpeak: Drop USB3 settings from devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81930?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: sb/intel/ibexpeak: Drop USB3 settings from devicetree
......................................................................

sb/intel/ibexpeak: Drop USB3 settings from devicetree

ibexpeak has no USB 3 capabilities.

They were kept briefly when its devicetree structure was split from
bd82x6x in commit ab4de83f4330 ("sb/intel/ibexpeak: Sever bd82x6x
source dependency") to verify correctness. With that done, they
can go.

Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
---
M src/southbridge/intel/ibexpeak/chip.h
1 file changed, 0 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Singer: Looks good to me, approved

diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h
index aba27cc..dc97da3 100644
--- a/src/southbridge/intel/ibexpeak/chip.h
+++ b/src/southbridge/intel/ibexpeak/chip.h
@@ -68,12 +68,6 @@

bool pcie_hotplug_map[8];

-	/* These USB3 fields, copied from bd82x6x, don't apply here,
-	 * as Ibex Peak doesn't have USB3. */
-	uint32_t xhci_switchable_ports;
-	uint32_t superspeed_capable_ports;
-	uint32_t xhci_overcurrent_mapping;
-
    uint32_t spi_uvscc;
    uint32_t spi_lvscc;
    struct intel_swseq_spi_config spi;